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arch/arm/src/common/stm32: enable backup domain access for LSI on U5
On U5 LSION is in RCC_BDCR, which is write-protected after reset. Without PWR DBP set the LSION write is ignored and stm32_rcc_enablelsi() waits forever for LSIRDY. - Add STM32_HAVE_IP_PWR_M33_V1 (U5) to the common PWR register dispatcher and the common stm32_pwr.h, so common code can reach the U5 PWR definitions and stm32_pwr_enablebkp(). - Rename stm32u5/hardware/stm32_pwr.h to stm32u5xx_pwr.h, so the common dispatcher can include it. - In stm32_lsi.c enable backup domain write access around the BDCR update, as the common LSE drivers do. Signed-off-by: raiden00pl <raiden00@railab.me> Assisted-by: Claude Code
This commit is contained in:
raiden00pl
Xiang Xiao
parent
a98162efc6
commit
db514c3e63
8 changed files with 45 additions and 7 deletions
2
.github/CODEOWNERS
vendored
2
.github/CODEOWNERS
vendored
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@ -4568,7 +4568,6 @@ arch/arm/src/stm32u5/hardware/stm32_gpio.h mijung@gmx.net alin.jerpelea@sony.com
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arch/arm/src/stm32u5/hardware/stm32_i2c.h cheshmedzhiev@gmail.com alin.jerpelea@sony.com
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arch/arm/src/stm32u5/hardware/stm32_memorymap.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com
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arch/arm/src/stm32u5/hardware/stm32_pinmap.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com
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arch/arm/src/stm32u5/hardware/stm32_pwr.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/src/stm32u5/hardware/stm32_rcc.h cheshmedzhiev@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com
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arch/arm/src/stm32u5/hardware/stm32_spi.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com
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arch/arm/src/stm32u5/hardware/stm32_syscfg.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com
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@ -4576,6 +4575,7 @@ arch/arm/src/stm32u5/hardware/stm32_tim.h mijung@gmx.net devel@sumpfralle.de ali
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arch/arm/src/stm32u5/hardware/stm32_uart.h mijung@gmx.net alin.jerpelea@sony.com
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arch/arm/src/stm32u5/hardware/stm32u5xx_dbgmcu.h cheshmedzhiev@gmail.com alin.jerpelea@sony.com
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arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h cheshmedzhiev@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com
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arch/arm/src/stm32u5/hardware/stm32u5xx_pwr.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h cheshmedzhiev@gmail.com 101105604+simbit18@users.noreply.github.com alin.jerpelea@sony.com
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arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h cheshmedzhiev@gmail.com 101105604+simbit18@users.noreply.github.com alin.jerpelea@sony.com
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arch/arm/src/stm32u5/stm32.h mijung@gmx.net alin.jerpelea@sony.com
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@ -630,6 +630,9 @@ config STM32_HAVE_IP_PWR_G0
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config STM32_HAVE_IP_PWR_M3M4_V1
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bool
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config STM32_HAVE_IP_PWR_M33_V1
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bool
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config STM32_HAVE_SMPS
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bool
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@ -29,7 +29,8 @@
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#if (defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + \
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defined(CONFIG_STM32_HAVE_IP_PWR_G0) + \
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defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)) > 1
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defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) + \
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defined(CONFIG_STM32_HAVE_IP_PWR_M33_V1)) > 1
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# error Only one STM32 PWR IP version must be selected
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#endif
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@ -38,6 +39,8 @@
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# include "hardware/stm32_pwr_v1_m0_g0.h"
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#elif defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)
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# include "hardware/stm32_pwr_v1.h"
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#elif defined(CONFIG_STM32_HAVE_IP_PWR_M33_V1)
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# include "hardware/stm32u5xx_pwr.h"
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#else
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# error "Unsupported STM32 PWR"
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#endif
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@ -29,6 +29,10 @@
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#include "arm_internal.h"
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#include "stm32_rcc.h"
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#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1
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# include "stm32_pwr.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@ -83,6 +87,15 @@
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void stm32_rcc_enablelsi(void)
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{
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#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1
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/* The LSI is in the backup domain and write access is denied to this
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* domain after reset, you have to enable write access using DBP bit in
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* the PWR register before configuring the LSI.
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*/
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stm32_pwr_enablebkp(true);
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#endif
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/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
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* bit in the controlling RCC register.
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*/
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@ -92,6 +105,12 @@ void stm32_rcc_enablelsi(void)
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/* Wait for the internal LSI oscillator to be stable. */
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while ((getreg32(STM32_RCC_LSI_REG) & RCC_LSI_LSIRDY) == 0);
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#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1
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/* Disable backup domain access */
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stm32_pwr_enablebkp(false);
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#endif
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}
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/****************************************************************************
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@ -104,11 +123,19 @@ void stm32_rcc_enablelsi(void)
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void stm32_rcc_disablelsi(void)
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{
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#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1
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stm32_pwr_enablebkp(true);
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#endif
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/* Disable the Internal Low-Speed (LSI) RC Oscillator by resetting the
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* LSION bit in the controlling RCC register.
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*/
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modifyreg32(STM32_RCC_LSI_REG, RCC_LSI_LSION, 0);
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#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1
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stm32_pwr_enablebkp(false);
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#endif
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/* LSIRDY should go low after 3 LSI clock cycles */
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}
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@ -124,7 +124,11 @@ void stm32_pwr_initbkp(bool writable);
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1
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bool stm32_pwr_enablebkp(bool writable);
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#else
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void stm32_pwr_enablebkp(bool writable);
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#endif
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/****************************************************************************
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* Name: stm32_pwr_enablewkup
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@ -73,6 +73,7 @@ config STM32_U5_PERIPHERALS
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select STM32_HAVE_CRC
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select STM32_HAVE_PWR
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select STM32_HAVE_BKPSRAM
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select STM32_HAVE_IP_PWR_M33_V1
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select STM32_HAVE_IP_WDG_M3M4_V1
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choice
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/stm32u5/hardware/stm32_pwr.h
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* arch/arm/src/stm32u5/hardware/stm32u5xx_pwr.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -20,8 +20,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H
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#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H
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#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PWR_H
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#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PWR_H
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/****************************************************************************
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* Included Files
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@ -202,4 +202,4 @@
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#define PWR_SVMSR_VDDA1RDY (1 << 26) /* Bit 26: V_DDA is equal or above ~1.6V */
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#define PWR_SVMSR_VDDA2RDY (1 << 27) /* Bit 27: V_DDA is equal or above ~1.8V */
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#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H */
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#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PWR_H */
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@ -32,7 +32,7 @@
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#include <stdbool.h>
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#include "chip.h"
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#include "hardware/stm32_pwr.h"
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#include "hardware/stm32u5xx_pwr.h"
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/****************************************************************************
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* Pre-processor Definitions
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