From db514c3e63a3d1d27d9563b89c826ee97d4a7f01 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 8 Oct 2026 12:45:03 +0200 Subject: [PATCH] arch/arm/src/common/stm32: enable backup domain access for LSI on U5 On U5 LSION is in RCC_BDCR, which is write-protected after reset. Without PWR DBP set the LSION write is ignored and stm32_rcc_enablelsi() waits forever for LSIRDY. - Add STM32_HAVE_IP_PWR_M33_V1 (U5) to the common PWR register dispatcher and the common stm32_pwr.h, so common code can reach the U5 PWR definitions and stm32_pwr_enablebkp(). - Rename stm32u5/hardware/stm32_pwr.h to stm32u5xx_pwr.h, so the common dispatcher can include it. - In stm32_lsi.c enable backup domain write access around the BDCR update, as the common LSE drivers do. Signed-off-by: raiden00pl Assisted-by: Claude Code --- .github/CODEOWNERS | 2 +- arch/arm/src/common/stm32/Kconfig.have | 3 +++ .../arm/src/common/stm32/hardware/stm32_pwr.h | 5 +++- arch/arm/src/common/stm32/stm32_lsi.c | 27 +++++++++++++++++++ arch/arm/src/common/stm32/stm32_pwr.h | 4 +++ arch/arm/src/stm32u5/Kconfig | 1 + .../hardware/{stm32_pwr.h => stm32u5xx_pwr.h} | 8 +++--- arch/arm/src/stm32u5/stm32_pwr.h | 2 +- 8 files changed, 45 insertions(+), 7 deletions(-) rename arch/arm/src/stm32u5/hardware/{stm32_pwr.h => stm32u5xx_pwr.h} (98%) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 80263516e4a..6ed1b9ae240 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -4568,7 +4568,6 @@ arch/arm/src/stm32u5/hardware/stm32_gpio.h mijung@gmx.net alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32_i2c.h cheshmedzhiev@gmail.com alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32_memorymap.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com arch/arm/src/stm32u5/hardware/stm32_pinmap.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32u5/hardware/stm32_pwr.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32u5/hardware/stm32_rcc.h cheshmedzhiev@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com arch/arm/src/stm32u5/hardware/stm32_spi.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com arch/arm/src/stm32u5/hardware/stm32_syscfg.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com @@ -4576,6 +4575,7 @@ arch/arm/src/stm32u5/hardware/stm32_tim.h mijung@gmx.net devel@sumpfralle.de ali arch/arm/src/stm32u5/hardware/stm32_uart.h mijung@gmx.net alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32u5xx_dbgmcu.h cheshmedzhiev@gmail.com alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h cheshmedzhiev@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com +arch/arm/src/stm32u5/hardware/stm32u5xx_pwr.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h cheshmedzhiev@gmail.com 101105604+simbit18@users.noreply.github.com alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h cheshmedzhiev@gmail.com 101105604+simbit18@users.noreply.github.com alin.jerpelea@sony.com arch/arm/src/stm32u5/stm32.h mijung@gmx.net alin.jerpelea@sony.com diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index 88b57a37df9..0c9b98dcd17 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -630,6 +630,9 @@ config STM32_HAVE_IP_PWR_G0 config STM32_HAVE_IP_PWR_M3M4_V1 bool +config STM32_HAVE_IP_PWR_M33_V1 + bool + config STM32_HAVE_SMPS bool diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr.h index cbd743564b8..2e039757d65 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_pwr.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr.h @@ -29,7 +29,8 @@ #if (defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + \ defined(CONFIG_STM32_HAVE_IP_PWR_G0) + \ - defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)) > 1 + defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_M33_V1)) > 1 # error Only one STM32 PWR IP version must be selected #endif @@ -38,6 +39,8 @@ # include "hardware/stm32_pwr_v1_m0_g0.h" #elif defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) # include "hardware/stm32_pwr_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_PWR_M33_V1) +# include "hardware/stm32u5xx_pwr.h" #else # error "Unsupported STM32 PWR" #endif diff --git a/arch/arm/src/common/stm32/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi.c index 8a8dea2f13e..cecaa5f9032 100644 --- a/arch/arm/src/common/stm32/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi.c @@ -29,6 +29,10 @@ #include "arm_internal.h" #include "stm32_rcc.h" +#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1 +# include "stm32_pwr.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -83,6 +87,15 @@ void stm32_rcc_enablelsi(void) { +#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1 + /* The LSI is in the backup domain and write access is denied to this + * domain after reset, you have to enable write access using DBP bit in + * the PWR register before configuring the LSI. + */ + + stm32_pwr_enablebkp(true); +#endif + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit in the controlling RCC register. */ @@ -92,6 +105,12 @@ void stm32_rcc_enablelsi(void) /* Wait for the internal LSI oscillator to be stable. */ while ((getreg32(STM32_RCC_LSI_REG) & RCC_LSI_LSIRDY) == 0); + +#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1 + /* Disable backup domain access */ + + stm32_pwr_enablebkp(false); +#endif } /**************************************************************************** @@ -104,11 +123,19 @@ void stm32_rcc_enablelsi(void) void stm32_rcc_disablelsi(void) { +#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1 + stm32_pwr_enablebkp(true); +#endif + /* Disable the Internal Low-Speed (LSI) RC Oscillator by resetting the * LSION bit in the controlling RCC register. */ modifyreg32(STM32_RCC_LSI_REG, RCC_LSI_LSION, 0); +#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1 + stm32_pwr_enablebkp(false); +#endif + /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/common/stm32/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_pwr.h index 4e41b05c465..f335ae63d87 100644 --- a/arch/arm/src/common/stm32/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_pwr.h @@ -124,7 +124,11 @@ void stm32_pwr_initbkp(bool writable); * ****************************************************************************/ +#ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1 +bool stm32_pwr_enablebkp(bool writable); +#else void stm32_pwr_enablebkp(bool writable); +#endif /**************************************************************************** * Name: stm32_pwr_enablewkup diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 7e8198aaa13..9a59eaf07e9 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -73,6 +73,7 @@ config STM32_U5_PERIPHERALS select STM32_HAVE_CRC select STM32_HAVE_PWR select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_PWR_M33_V1 select STM32_HAVE_IP_WDG_M3M4_V1 choice diff --git a/arch/arm/src/stm32u5/hardware/stm32_pwr.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_pwr.h similarity index 98% rename from arch/arm/src/stm32u5/hardware/stm32_pwr.h rename to arch/arm/src/stm32u5/hardware/stm32u5xx_pwr.h index 27626af188f..656223e0beb 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32u5/hardware/stm32_pwr.h + * arch/arm/src/stm32u5/hardware/stm32u5xx_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PWR_H +#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PWR_H /**************************************************************************** * Included Files @@ -202,4 +202,4 @@ #define PWR_SVMSR_VDDA1RDY (1 << 26) /* Bit 26: V_DDA is equal or above ~1.6V */ #define PWR_SVMSR_VDDA2RDY (1 << 27) /* Bit 27: V_DDA is equal or above ~1.8V */ -#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PWR_H */ diff --git a/arch/arm/src/stm32u5/stm32_pwr.h b/arch/arm/src/stm32u5/stm32_pwr.h index 97da688453d..995b54c4cd4 100644 --- a/arch/arm/src/stm32u5/stm32_pwr.h +++ b/arch/arm/src/stm32u5/stm32_pwr.h @@ -32,7 +32,7 @@ #include #include "chip.h" -#include "hardware/stm32_pwr.h" +#include "hardware/stm32u5xx_pwr.h" /**************************************************************************** * Pre-processor Definitions