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adc_shutdown() gates the ADC clock (RCU_APB2EN.ADCEN) when the device is closed, but the one-shot adc_reset() that first enabled it only runs at registration and adc_setup() never re-enabled it. A second open() then drove a clock-gated peripheral whose conversions never completed, so a second run of a reader such as the adc example hung after opening the device. adc_setup() now re-enables the ADC clock; clock gating preserves the register configuration, so nothing else has to be re-programmed. Add an "adc" configuration that exercises the driver. It is the nsh base plus the ADC driver, registered as /dev/adc0 and read by the adc example. ADC channel 8 (ADC_IN8) is routed to PB0 on the J1 header so an analog voltage applied there is sampled. The board bringup samples that channel when the pin is routed, and PB0 is only claimed for the ADC when SPI is off (with SPI on it belongs to the I2C0 fallback), so the periph configuration is unaffected. The GD32VW55x ADC converts on demand rather than continuously, so the example uses the software trigger (CONFIG_EXAMPLES_ADC_SWTRIG) and is bounded to 20 sample groups so it returns to the prompt. Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| dummy | ||
| hc/m9s12 | ||
| mips | ||
| misoc/lm32/misoc | ||
| or1k/mor1kx/or1k | ||
| renesas | ||
| risc-v | ||
| sim/sim/sim | ||
| sparc | ||
| tricore | ||
| x86/qemu/qemu-i486 | ||
| x86_64/qemu/qemu-intel64 | ||
| xtensa | ||
| z16/z16f/z16f2800100zcog | ||
| z80 | ||
| .gitignore | ||
| Board.mk | ||
| boardctl.c | ||
| CMakeLists.txt | ||
| dummy.c | ||
| Kconfig | ||
| Makefile | ||