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!sched/clock: remove CONFIG_SYSTEM_TIME64 and always use 64-bit time

Browse source 
The 32-bit system clock has a limited range (~497 days) and the
configuration knob is no longer worth the complexity given that
practically every modern target already enables it.  Make 64-bit
time_t/clock_t/sclock_t/nuttx_time_t the only supported flavor.

Specifically:
  - Drop the SYSTEM_TIME64 Kconfig option and its dependent
    PERF_OVERFLOW_CORRECTION/HRTIMER guards in sched/Kconfig.
  - Remove every #ifdef CONFIG_SYSTEM_TIME64 branch in headers
    (include/{sys/types.h,limits.h,inttypes.h,nuttx/clock.h,
    nuttx/fs/hostfs.h}) and core code paths
    (sched/clock/clock.h, drivers/power/pm/pm_procfs.c,
    drivers/rpmsg/rpmsg_ping.c, fs/procfs/fs_procfsuptime.c,
    libs/libc/wqueue/work_usrthread.c,
    arch/avr/src/avrdx/avrdx_timerisr_tickless_alarm.c).
  - Strip CONFIG_SYSTEM_TIME64=y from every board defconfig.
  - Update Documentation/guides/rust.rst accordingly.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2026-05-03 15:54:17 +08:00 • committed by Xiang Xiao
parent 1b3af76bf3
commit c6654b1106
187 changed files with 147 additions and 338 deletions
Download patch file Download diff file Expand all files Collapse all files

1
Documentation/guides/rust.rst
View file

@ -57,7 +57,6 @@ Please ensure that you have a working NuttX build environment, and with the foll
Please enable the following configurations in your NuttX configuration:
- CONFIG_SYSTEM_TIME64
- CONFIG_FS_LARGEFILE
- CONFIG_TLS_NELEM = 16
- CONFIG_DEV_URANDOM

2
arch/arm/src/armv7-a/arm_perf.c
View file

@ -95,6 +95,6 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
ts->tv_sec = elapsed / g_cpu_freq;
left = elapsed - ts->tv_sec * g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * left / g_cpu_freq;
}
#endif

2
arch/arm/src/armv7-m/arm_perf.c
View file

@ -76,6 +76,6 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
ts->tv_sec = elapsed / g_cpu_freq;
left = elapsed - ts->tv_sec * g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * left / g_cpu_freq;
}
#endif

2
arch/arm/src/armv7-r/arm_perf.c
View file

@ -91,7 +91,7 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
ts->tv_sec = elapsed / g_cpu_freq;
left = elapsed - ts->tv_sec * g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * left / g_cpu_freq;
}
#endif /* CONFIG_BUILD_FLAT || __KERNEL__ */

2
arch/arm/src/armv8-m/arm_perf.c
View file

@ -76,6 +76,6 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
ts->tv_sec = elapsed / g_cpu_freq;
left = elapsed - ts->tv_sec * g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * left / g_cpu_freq;
}
#endif

2
arch/arm/src/armv8-r/arm_perf.c
View file

@ -87,6 +87,6 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
ts->tv_sec = elapsed / g_cpu_freq;
left = elapsed - ts->tv_sec * g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * left / g_cpu_freq;
}
#endif /* CONFIG_ARCH_PERF_EVENTS */

2
arch/arm/src/cxd56xx/cxd56_cisif.c
View file

@ -288,7 +288,7 @@ static uint64_t cisif_get_msec_time(void)
clock_systime_timespec(&tp);
return (((uint64_t)tp.tv_sec) * 1000 + tp.tv_nsec / 1000000);
return tp.tv_sec * 1000 + tp.tv_nsec / 1000000;
}
static void cisif_trace_time_start(void)

8
arch/arm/src/cxd56xx/cxd56_nxaudio.c
View file

@ -2096,8 +2096,8 @@ static int cxd56_power_on_micbias(struct cxd56_dev_s *dev)
clock_systime_timespec(&start);
dev->mic_boot_start = (uint64_t)start.tv_sec * 1000 +
(uint64_t)start.tv_nsec / 1000000;
dev->mic_boot_start = start.tv_sec * 1000 +
start.tv_nsec / 1000000;
return OK;
}
@ -2951,8 +2951,8 @@ static int cxd56_start(struct audio_lowerhalf_s *lower)
clock_systime_timespec(&end);
uint64_t time = (uint64_t)end.tv_sec * 1000 +
(uint64_t)end.tv_nsec / 1000000 -
uint64_t time = end.tv_sec * 1000 +
end.tv_nsec / 1000000 -
priv->mic_boot_start;
if (time < CXD56_MIC_BOOT_WAIT)

2
arch/arm/src/cxd56xx/cxd56_rtc.c
View file

@ -481,7 +481,7 @@ int up_rtc_settime(const struct timespec *tp)
/* Only save the difference from HW raw value */
count = SEC_TO_CNT(tp->tv_sec) | NSEC_TO_PRECNT(tp->tv_nsec);
g_rtc_save->offset = (int64_t)count - (int64_t)cxd56_rtc_count();
g_rtc_save->offset = count - cxd56_rtc_count();
#endif
cxd56_update_basetime(&g_basetime);

2
arch/arm/src/efm32/efm32_rtc_burtc.c
View file

@ -466,7 +466,7 @@ int up_rtc_settime(const struct timespec *tp)
/* Compute Burtc offset because we cannot reset counter */
val = (((uint64_t)tp->tv_sec) * CONFIG_RTC_FREQUENCY) + \
val = (tp->tv_sec * CONFIG_RTC_FREQUENCY) + \
(tp->tv_nsec / (NSEC_PER_SEC / CONFIG_RTC_FREQUENCY));
if (val < cnt_reg)

2
arch/arm/src/imxrt/imxrt_tickless.c
View file

@ -501,7 +501,7 @@ int up_timer_gettime(struct timespec *ts)
int up_alarm_start(const struct timespec *ts)
{
size_t offset = 1;
uint64_t tm = ((uint64_t)ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
uint64_t tm = (ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
NSEC_PER_TICK;
irqstate_t flags;
uint32_t regval;

2
arch/arm/src/lc823450/lc823450_dvfs2.c
View file

@ -131,7 +131,7 @@ static uint64_t _get_current_time64(void)
struct timespec ts;
clock_systime_timespec(&ts);
return (uint64_t)ts.tv_sec * NSEC_PER_SEC + (uint64_t)ts.tv_nsec;
return ts.tv_sec * NSEC_PER_SEC + ts.tv_nsec;
}
/****************************************************************************

2
arch/arm/src/lc823450/lc823450_timer.c
View file

@ -706,7 +706,7 @@ int up_rtc_gettime(struct timespec *tp)
/* Get the elapsed time */
elapsed = NSEC_PER_TICK * (uint64_t)clock_systime_ticks();
elapsed = NSEC_PER_TICK * clock_systime_ticks();
/* Add the timer fraction in nanoseconds */

2
arch/arm/src/lpc31xx/lpc31_timerisr.c
View file

@ -111,7 +111,7 @@ void up_timer_initialize(void)
freq >>= 4;
}
load = ((freq * (uint64_t)10000) / 1000000);
load = ((freq * 10000) / 1000000);
putreg32((uint32_t)load, LPC31_TIMER0_LOAD);
/* Set periodic mode */

8
arch/arm/src/lpc43xx/lpc43_rit.c
View file

@ -81,7 +81,7 @@ static int lpc43_rit_isr(int irq, void *context, void *arg)
putreg32(RIT_CTRL_INT, LPC43_RIT_CTRL);
g_internal_timer += (uint64_t)RIT_TIMER_RESOLUTION;
g_internal_timer += RIT_TIMER_RESOLUTION;
if (g_alarm > 0 && g_internal_timer >= g_alarm)
{
/* handle expired alarm */
@ -228,8 +228,7 @@ int up_alarm_start(const struct timespec *ts)
* coded.
*/
g_alarm = (uint64_t)ts->tv_sec * (uint64_t)1000000000 +
(uint64_t)ts->tv_nsec;
g_alarm = ts->tv_sec * 1000000000 + ts->tv_nsec;
return OK;
}
@ -252,8 +251,7 @@ int up_timer_start(const struct timespec *ts)
*/
g_alarm = g_internal_timer;
g_alarm += (uint64_t)ts->tv_sec * (uint64_t)1000000000 +
(uint64_t)ts->tv_nsec;
g_alarm += ts->tv_sec * 1000000000 + ts->tv_nsec;
return OK;
}

4
arch/arm/src/lpc54xx/lpc54_tickless.c
View file

@ -273,8 +273,8 @@ static void lpc54_ts_sub(const struct timespec *ts1,
static inline uint64_t lpc54_ts2tick(const struct timespec *ts)
{
return ((uint64_t)ts->tv_sec * LPC54_CCLK +
((uint64_t)ts->tv_nsec / g_min_nsec * g_min_ticks));
return (ts->tv_sec * LPC54_CCLK +
(ts->tv_nsec / g_min_nsec * g_min_ticks));
}
static uint64_t lpc54_tick2ts(uint64_t ticks, struct timespec *ts,

4
arch/arm/src/sam34/sam4cm_oneshot.c
View file

@ -289,8 +289,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.

6
arch/arm/src/sama5/sam_oneshot.c
View file

@ -299,8 +299,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec *
USEC_PER_SEC + (uint64_t)(ts->tv_nsec /
usec = ts->tv_sec *
USEC_PER_SEC + (ts->tv_nsec /
NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts
@ -311,7 +311,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
* = (usecs * frequency) / USEC_PER_SEC;
*/
regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC;
regval = (usec * sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC;
tmrinfo("usec=%llu regval=%08llx\n", usec, regval);
DEBUGASSERT(regval <= UINT32_MAX);

3
arch/arm/src/samd5e5/sam_oneshot.c
View file

@ -233,8 +233,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec /
NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC + (ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine
* the number of counts need to achieve the requested delay.

4
arch/arm/src/samv7/sam_oneshot.c
View file

@ -300,8 +300,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts
* needed to achieve the requested delay.

4
arch/arm/src/stm32/stm32_oneshot.c
View file

@ -283,8 +283,8 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.

2
arch/arm/src/stm32/stm32_rtcounter.c
View file

@ -296,7 +296,7 @@ static void stm32_rtc_breakout(const struct timespec *tp,
* our use
*/
frac = ((uint64_t)tp->tv_nsec * CONFIG_RTC_FREQUENCY) / 1000000000;
frac = (tp->tv_nsec * CONFIG_RTC_FREQUENCY) / 1000000000;
cnt = (tp->tv_sec << RTC_CLOCKS_SHIFT) |
((uint32_t)frac & (CONFIG_RTC_FREQUENCY - 1));
ovf = (tp->tv_sec >> (32 - RTC_CLOCKS_SHIFT));

4
arch/arm/src/stm32/stm32_tickless.c
View file

@ -929,8 +929,8 @@ int up_timer_start(const struct timespec *ts)
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.

6
arch/arm/src/stm32f7/stm32_tickless.c
View file

@ -973,8 +973,8 @@ int up_timer_start(const struct timespec *ts)
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.
@ -1021,7 +1021,7 @@ int up_timer_start(const struct timespec *ts)
int up_alarm_start(const struct timespec *ts)
{
size_t offset = 1;
uint64_t tm = ((uint64_t)ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
uint64_t tm = (ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
NSEC_PER_TICK;
irqstate_t flags;

4
arch/arm/src/stm32h7/stm32_oneshot.c
View file

@ -286,8 +286,8 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.

6
arch/arm/src/stm32h7/stm32_tickless.c
View file

@ -947,8 +947,8 @@ int up_timer_start(const struct timespec *ts)
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.
@ -995,7 +995,7 @@ int up_timer_start(const struct timespec *ts)
int up_alarm_start(const struct timespec *ts)
{
size_t offset = 1;
uint64_t tm = ((uint64_t)ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
uint64_t tm = (ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
NSEC_PER_TICK;
irqstate_t flags;

4
arch/arm/src/stm32l4/stm32l4_oneshot.c
View file

@ -284,8 +284,8 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.

4
arch/arm/src/stm32wb/stm32wb_oneshot.c
View file

@ -284,8 +284,8 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.

4
arch/arm/src/stm32wb/stm32wb_tickless.c
View file

@ -795,8 +795,8 @@ int up_timer_start(const struct timespec *ts)
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.

4
arch/arm/src/xmc4/xmc4_tickless.c
View file

@ -429,8 +429,8 @@ int up_timer_start(const struct timespec *ts)
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Compute periods of the timers to match delay to wait */

3
arch/avr/src/avrdx/avrdx_timerisr_tickless_alarm.c
View file

@ -301,8 +301,7 @@ static void avrdx_check_alarm_expired(uint8_t context)
/* Note about data types - struct timespec is defined
* in include/time.h, tv_sec is of type time_t which is defined
* in include/sys/types.h as uint32_t or uint64_t based
* on CONFIG_SYSTEM_TIME64
* in include/sys/types.h as uint64_t.
*
* tv_nsec is defined as long, signed value
*/

6
arch/mips/src/pic32mz/pic32mz_oneshot.c
View file

@ -302,10 +302,10 @@ int pic32mz_oneshot_start(struct pic32mz_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
period = (usec * (uint64_t)oneshot->freq) / USEC_PER_SEC;
period = (usec * oneshot->freq) / USEC_PER_SEC;
tmrinfo("usec=%llu period=%08llx\n", usec, period);
DEBUGASSERT(period <= ((1ull << oneshot->width) - 1ul));

2
arch/mips/src/pic32mz/pic32mz_timer_lowerhalf.c
View file

@ -199,7 +199,7 @@ static uint32_t pic32mz_usec2ticks(struct pic32mz_lowerhalf_s *priv,
{
uint64_t bigticks;
bigticks = ((uint64_t)usecs * (uint64_t)priv->freq) / 1000000;
bigticks = (usecs * priv->freq) / 1000000;
if (bigticks > UINT32_MAX)
{

2
arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
View file

@ -124,7 +124,7 @@ static inline uint64_t bl602_get_nsec(void)
up_timer_gettime(&ts);
return (uint64_t)ts.tv_nsec + (uint64_t)ts.tv_sec * NSEC_PER_SEC;
return ts.tv_nsec + ts.tv_sec * NSEC_PER_SEC;
}
/****************************************************************************

4
arch/risc-v/src/common/espressif/esp_i2c.c
View file

@ -1510,7 +1510,7 @@ static void esp_i2c_tracedump(struct esp_i2c_priv_s *priv)
struct esp_trace_s *trace;
int i;
syslog(LOG_DEBUG, "Elapsed time: %" PRIu32 "\n",
syslog(LOG_DEBUG, "Elapsed time: %" PRId64 "\n",
(clock_systime_ticks() - priv->start_time));
for (i = 0; i < priv->tndx; i++)
@ -1518,7 +1518,7 @@ static void esp_i2c_tracedump(struct esp_i2c_priv_s *priv)
trace = &priv->trace[i];
syslog(LOG_DEBUG,
"%2d. STATUS: %08" PRIx32 " COUNT: %3" PRIu32 " EVENT: %s(%2d)"
" PARM: %08" PRIx32 " TIME: %" PRIu32 "\n",
" PARM: %08" PRIx32 " TIME: %" PRId64 "\n",
i + 1, trace->status, trace->count, g_trace_names[trace->event],
trace->event, trace->parm, trace->time - priv->start_time);
}

2
arch/risc-v/src/common/espressif/esp_rtc.c
View file

@ -775,7 +775,7 @@ int up_rtc_settime(const struct timespec *ts)
flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock);
now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC +
now_us = ts->tv_sec * USEC_PER_SEC +
ts->tv_nsec / NSEC_PER_USEC;
#ifdef CONFIG_RTC_DRIVER

4
arch/risc-v/src/common/espressif/esp_tickless.c
View file

@ -359,8 +359,8 @@ int IRAM_ATTR up_timer_start(const struct timespec *ts)
up_timer_cancel(NULL);
}
target_us = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
target_us = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
alarm_ticks = systimer_hal_get_counter_value(&systimer_hal,
SYSTIMER_COUNTER_OS_TICK);

4
arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c
View file

@ -1281,7 +1281,7 @@ static void esp32c3_i2c_tracedump(struct esp32c3_i2c_priv_s *priv)
struct esp32c3_trace_s *trace;
int i;
syslog(LOG_DEBUG, "Elapsed time: %" PRIu32 "\n",
syslog(LOG_DEBUG, "Elapsed time: %" PRId64 "\n",
(clock_systime_ticks() - priv->start_time));
for (i = 0; i < priv->tndx; i++)
@ -1289,7 +1289,7 @@ static void esp32c3_i2c_tracedump(struct esp32c3_i2c_priv_s *priv)
trace = &priv->trace[i];
syslog(LOG_DEBUG,
"%2d. STATUS: %08" PRIx32 " COUNT: %3" PRIu32 " EVENT: %s(%2d)"
" PARM: %08" PRIx32 " TIME: %" PRIu32 "\n",
" PARM: %08" PRIx32 " TIME: %" PRId64 "\n",
i + 1, trace->status, trace->count, g_trace_names[trace->event],
trace->event, trace->parm, trace->time - priv->start_time);
}

6
arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.c
View file

@ -283,8 +283,8 @@ int esp32c3_oneshot_start(struct esp32c3_oneshot_s *oneshot,
/* Retrieve the duration from timespec in microsecond */
timeout_us = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
timeout_us = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Verify if it is a multiple of the configured resolution.
* In case it isn't, warn the user.
@ -452,7 +452,7 @@ int esp32c3_oneshot_current(struct esp32c3_oneshot_s *oneshot,
ESP32C3_TIM_GETCTR(oneshot->tim, usec);
*usec = *usec * (uint64_t)oneshot->resolution;
*usec = *usec * oneshot->resolution;
return OK;
}

4
arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c
View file

@ -444,8 +444,8 @@ static uint32_t IRAM_ATTR esp32c3_get_power_down_flags(void)
static void IRAM_ATTR esp32c3_timer_wakeup_prepare(void)
{
int64_t ticks;
int64_t sleep_duration = (int64_t)s_config.sleep_duration -
(int64_t) s_config.sleep_time_adjustment;
int64_t sleep_duration = s_config.sleep_duration -
s_config.sleep_time_adjustment;
if (sleep_duration < 0)
{
sleep_duration = 0;

2
arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c
View file

@ -3136,7 +3136,7 @@ int up_rtc_settime(const struct timespec *ts)
DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC);
flags = spin_lock_irqsave(&g_rtc_lock);
now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC +
now_us = ts->tv_sec * USEC_PER_SEC +
ts->tv_nsec / NSEC_PER_USEC;
if (g_rt_timer_enabled == true)
{

4
arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.c
View file

@ -453,8 +453,8 @@ int IRAM_ATTR up_timer_start(const struct timespec *ts)
up_timer_cancel(NULL);
}
cpu_ticks = SEC_2_CTICK((uint64_t)ts->tv_sec) +
NSEC_2_CTICK((uint64_t)ts->tv_nsec);
cpu_ticks = SEC_2_CTICK(ts->tv_sec) +
NSEC_2_CTICK(ts->tv_nsec);
up_tmr_setcounter(cpu_ticks);
g_timer_started = true;

2
arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.c
View file

@ -386,7 +386,7 @@ static int esp32c3_timer_settimeout(struct timer_lowerhalf_s *lower,
/* Set the timeout */
ESP32C3_TIM_SETALRVL(priv->tim, (uint64_t)timeout);
ESP32C3_TIM_SETALRVL(priv->tim, timeout);
return ret;
}

2
arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c
View file

@ -2926,7 +2926,7 @@ static void wifi_rtc_disable_iso(void)
int64_t esp_timer_get_time(void)
{
return (int64_t)rt_timer_time_us();
return rt_timer_time_us();
}
/****************************************************************************

4
arch/risc-v/src/esp32c3/esp_ble_adapter.c
View file

@ -1585,7 +1585,7 @@ static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles,
uint64_t local_error_corr;
uint64_t res;
local_error_corr = (error_corr == NULL) ? 0 : (uint64_t)(*error_corr);
local_error_corr = (error_corr == NULL) ? 0 : (*error_corr);
res = (uint64_t)g_btdm_lpcycle_us * cycles * 2;
local_error_corr += res;
@ -2981,7 +2981,7 @@ static void coex_bt_wakeup_request_end(void)
static IRAM_ATTR int64_t get_time_us_wrapper(void)
{
return (int64_t)esp_hr_timer_time_us();
return esp_hr_timer_time_us();
}
/****************************************************************************

2
arch/risc-v/src/esp32c3/esp_coex_adapter.c
View file

@ -117,7 +117,7 @@ coex_adapter_funcs_t g_coex_adapter_funcs =
static IRAM_ATTR int64_t esp_coex_esp_timer_get_time_wrapper(void)
{
return (int64_t)esp_hr_timer_time_us();
return esp_hr_timer_time_us();
}
/****************************************************************************

2
arch/risc-v/src/esp32c6/esp_coex_adapter.c
View file

@ -114,7 +114,7 @@ coex_adapter_funcs_t g_coex_adapter_funcs =
static IRAM_ATTR int64_t esp_coex_esp_timer_get_time_wrapper(void)
{
return (int64_t)esp_hr_timer_time_us();
return esp_hr_timer_time_us();
}
/****************************************************************************

4
arch/risc-v/src/litex/litex_tickless.c
View file

@ -302,8 +302,8 @@ int up_timer_start(const struct timespec *ts)
litex_timer_cancel();
cpu_ticks = SEC_2_LITEX_TICK((uint64_t)ts->tv_sec) +
NSEC_2_LITEX_TICK((uint64_t)ts->tv_nsec);
cpu_ticks = SEC_2_LITEX_TICK(ts->tv_sec) +
NSEC_2_LITEX_TICK(ts->tv_nsec);
DEBUGASSERT(cpu_ticks <= UINT32_MAX);

4
arch/sparc/src/bm3803/bm3803_freerun.c
View file

@ -232,8 +232,8 @@ int bm3803_freerun_counter(struct bm3803_freerun_s *freerun,
ts->tv_sec = sec;
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
tmrinfo("usec=%llu ts=(%u, %lu)\n",
usec, ts->tv_sec, (unsigned long)ts->tv_nsec);
tmrinfo("usec=%llu ts=(%lld, %ld)\n",
usec, ts->tv_sec, ts->tv_nsec);
return OK;
}

6
arch/sparc/src/bm3803/bm3803_oneshot.c
View file

@ -229,8 +229,8 @@ int bm3803_oneshot_start(struct bm3803_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need
* to achieve the requested delay.
@ -240,7 +240,7 @@ int bm3803_oneshot_start(struct bm3803_oneshot_s *oneshot,
* = (usecs * frequency) / USEC_PER_SEC;
*/
period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC;
period = (usec * oneshot->frequency) / USEC_PER_SEC;
tmrinfo("usec=%llu period=%08llx\n", usec, period);
DEBUGASSERT(period <= UINT24_MAX);

6
arch/x86_64/src/intel64/intel64_oneshot.c
View file

@ -315,8 +315,8 @@ int intel64_oneshot_start(struct intel64_oneshot_s *oneshot,
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
usec = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* HPET use free running up-counter and a comparators which generate events
* only on a equal event. This can results in event miss if we set too
@ -337,7 +337,7 @@ int intel64_oneshot_start(struct intel64_oneshot_s *oneshot,
* = (usecs * frequency) / USEC_PER_SEC;
*/
compare = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC;
compare = (usec * oneshot->frequency) / USEC_PER_SEC;
#ifndef CONFIG_INTEL64_HPET_FSB
/* Set up to receive the callback when the interrupt occurs */

2
arch/x86_64/src/intel64/intel64_perf.c
View file

@ -64,7 +64,7 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
ts->tv_sec = elapsed / g_x86_64_timer_freq;
left = elapsed - ts->tv_sec * g_x86_64_timer_freq;
ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_x86_64_timer_freq;
ts->tv_nsec = NSEC_PER_SEC * left / g_x86_64_timer_freq;
}
#endif

2
arch/xtensa/src/common/espressif/esp_rtc.c
View file

@ -774,7 +774,7 @@ int up_rtc_settime(const struct timespec *ts)
flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock);
now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC +
now_us = ts->tv_sec * USEC_PER_SEC +
ts->tv_nsec / NSEC_PER_USEC;
#ifdef CONFIG_RTC_DRIVER

4
arch/xtensa/src/common/xtensa_oneshot.c
View file

@ -102,8 +102,8 @@ static int xtensa_oneshot_start(struct oneshot_lowerhalf_s *lower_,
flags = spin_lock_irqsave(&lower->lock);
count = sec_to_count((uint64_t)ts->tv_sec, lower->freq) +
nsec_to_count((uint64_t)ts->tv_nsec, lower->freq);
count = sec_to_count(ts->tv_sec, lower->freq) +
nsec_to_count(ts->tv_nsec, lower->freq);
count = xtensa_getcount() + count;
xtensa_setcompare(count);

2
arch/xtensa/src/common/xtensa_perf.c
View file

@ -63,6 +63,6 @@ void up_perf_convert(clock_t elapsed, struct timespec *ts)
ts->tv_sec = elapsed / g_cpu_freq;
left = elapsed - ts->tv_sec * g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
ts->tv_nsec = NSEC_PER_SEC * left / g_cpu_freq;
}
#endif

4
arch/xtensa/src/esp32/esp32_i2c.c
View file

@ -1279,7 +1279,7 @@ static void esp32_i2c_tracedump(struct esp32_i2c_priv_s *priv)
struct esp32_trace_s *trace;
int i;
syslog(LOG_DEBUG, "Elapsed time: %" PRIu32 "\n",
syslog(LOG_DEBUG, "Elapsed time: %" PRId64 "\n",
(clock_systime_ticks() - priv->start_time));
for (i = 0; i < priv->tndx; i++)
@ -1287,7 +1287,7 @@ static void esp32_i2c_tracedump(struct esp32_i2c_priv_s *priv)
trace = &priv->trace[i];
syslog(LOG_DEBUG,
"%2d. STATUS: %08" PRIx32 " COUNT: %3" PRIu32 " EVENT: %s(%2d)"
" PARM: %08" PRIx32 " TIME: %" PRIu32 "\n",
" PARM: %08" PRIx32 " TIME: %" PRId64 "\n",
i + 1, trace->status, trace->count, g_trace_names[trace->event],
trace->event, trace->parm, trace->time - priv->start_time);
}

6
arch/xtensa/src/esp32/esp32_oneshot.c
View file

@ -274,8 +274,8 @@ int esp32_oneshot_start(struct esp32_oneshot_s *oneshot,
/* Retrieve the duration from timespec in microsecond */
timeout_us = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
timeout_us = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Verify if it is a multiple of the configured resolution.
* In case it isn't, warn the user.
@ -443,7 +443,7 @@ int esp32_oneshot_current(struct esp32_oneshot_s *oneshot, uint64_t *usec)
ESP32_TIM_GETCTR(oneshot->tim, usec);
*usec = *usec * (uint64_t)oneshot->resolution;
*usec = *usec * oneshot->resolution;
return OK;
}

2
arch/xtensa/src/esp32/esp32_psram.c
View file

@ -993,7 +993,7 @@ static void psram_read_id(uint64_t *dev_id)
psram_cmd_recv_start(spi_num, ps_cmd.rx_data,
ps_cmd.rx_data_bit_len / 8, PSRAM_CMD_SPI);
psram_cmd_end(spi_num);
*dev_id = (uint64_t)(((uint64_t)psram_id[1] << 32) | psram_id[0]);
*dev_id = (((uint64_t)psram_id[1] << 32) | psram_id[0]);
}
/* enter QPI mode */

4
arch/xtensa/src/esp32/esp32_tickless.c
View file

@ -449,8 +449,8 @@ int IRAM_ATTR up_timer_start(const struct timespec *ts)
up_timer_cancel(NULL);
}
cpu_ticks = SEC_2_CTICK((uint64_t)ts->tv_sec) +
NSEC_2_CTICK((uint64_t)ts->tv_nsec);
cpu_ticks = SEC_2_CTICK(ts->tv_sec) +
NSEC_2_CTICK(ts->tv_nsec);
up_tmr_setcount(cpu_ticks);

2
arch/xtensa/src/esp32/esp32_tim_lowerhalf.c
View file

@ -408,7 +408,7 @@ static int esp32_timer_settimeout(struct timer_lowerhalf_s *lower,
/* Set the timeout */
ESP32_TIM_SETALRVL(priv->tim, (uint64_t)timeout);
ESP32_TIM_SETALRVL(priv->tim, timeout);
return ret;
}

2
arch/xtensa/src/esp32/esp32_wifi_adapter.c
View file

@ -2263,7 +2263,7 @@ static void wifi_rtc_disable_iso(void)
int64_t esp32_timer_get_time(void)
{
return (int64_t)esp_hr_timer_time_us();
return esp_hr_timer_time_us();
}
/****************************************************************************

4
arch/xtensa/src/esp32s2/esp32s2_i2c.c
View file

@ -1452,7 +1452,7 @@ static void i2c_traceevent(struct esp32s2_i2c_priv_s *priv,
#ifdef CONFIG_I2C_TRACE
static void i2c_tracedump(struct esp32s2_i2c_priv_s *priv)
{
syslog(LOG_DEBUG, "Elapsed time: %" PRIu32 "\n",
syslog(LOG_DEBUG, "Elapsed time: %" PRId64 "\n",
clock_systime_ticks() - priv->start_time);
for (int i = 0; i < priv->tndx; i++)
@ -1460,7 +1460,7 @@ static void i2c_tracedump(struct esp32s2_i2c_priv_s *priv)
struct esp32s2_trace_s *trace = &priv->trace[i];
syslog(LOG_DEBUG,
"%2d. STATUS: %08" PRIx32 " COUNT: %3" PRIu32 " EVENT: %s(%2d)"
" PARM: %08" PRIx32 " TIME: %" PRIu32 "\n",
" PARM: %08" PRIx32 " TIME: %" PRId64 "\n",
i + 1, trace->status, trace->count, g_trace_names[trace->event],
trace->event, trace->parm, trace->time - priv->start_time);
}

6
arch/xtensa/src/esp32s2/esp32s2_oneshot.c
View file

@ -288,8 +288,8 @@ int esp32s2_oneshot_start(struct esp32s2_oneshot_s *oneshot,
/* Retrieve the duration from timespec in microsecond */
timeout_us = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
timeout_us = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Verify if it is a multiple of the configured resolution.
* In case it isn't, warn the user.
@ -459,7 +459,7 @@ int esp32s2_oneshot_current(struct esp32s2_oneshot_s *oneshot,
ESP32S2_TIM_GETCTR(oneshot->tim, usec);
*usec = *usec * (uint64_t)oneshot->resolution;
*usec = *usec * oneshot->resolution;
return OK;
}

2
arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c
View file

@ -405,7 +405,7 @@ static int esp32s2_timer_settimeout(struct timer_lowerhalf_s *lower,
/* Set the timeout */
ESP32S2_TIM_SETALRVL(priv->tim, (uint64_t)timeout);
ESP32S2_TIM_SETALRVL(priv->tim, timeout);
return ret;
}

2
arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c
View file

@ -2081,7 +2081,7 @@ static void wifi_clock_disable(void)
int64_t esp32s2_timer_get_time(void)
{
return (int64_t)esp_hr_timer_time_us();
return esp_hr_timer_time_us();
}
/****************************************************************************

4
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
View file

@ -1569,7 +1569,7 @@ static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles,
uint64_t local_error_corr;
uint64_t res;
local_error_corr = (error_corr == NULL) ? 0 : (uint64_t)(*error_corr);
local_error_corr = (error_corr == NULL) ? 0 : (*error_corr);
res = (uint64_t)g_btdm_lpcycle_us * cycles * 2;
local_error_corr += res;
@ -2967,7 +2967,7 @@ static void coex_bt_wakeup_request_end(void)
static IRAM_ATTR int64_t get_time_us_wrapper(void)
{
return (int64_t)esp_hr_timer_time_us();
return esp_hr_timer_time_us();
}
/****************************************************************************

4
arch/xtensa/src/esp32s3/esp32s3_i2c.c
View file

@ -1484,7 +1484,7 @@ static void i2c_traceevent(struct esp32s3_i2c_priv_s *priv,
#ifdef CONFIG_I2C_TRACE
static void i2c_tracedump(struct esp32s3_i2c_priv_s *priv)
{
syslog(LOG_DEBUG, "Elapsed time: %" PRIu32 "\n",
syslog(LOG_DEBUG, "Elapsed time: %" PRId64 "\n",
clock_systime_ticks() - priv->start_time);
for (int i = 0; i < priv->tndx; i++)
@ -1492,7 +1492,7 @@ static void i2c_tracedump(struct esp32s3_i2c_priv_s *priv)
struct esp32s3_trace_s *trace = &priv->trace[i];
syslog(LOG_DEBUG,
"%2d. STATUS: %08" PRIx32 " COUNT: %3" PRIu32 " EVENT: %s(%2d)"
" PARM: %08" PRIx32 " TIME: %" PRIu32 "\n",
" PARM: %08" PRIx32 " TIME: %" PRId64 "\n",
i + 1, trace->status, trace->count, g_trace_names[trace->event],
trace->event, trace->parm, trace->time - priv->start_time);
}

6
arch/xtensa/src/esp32s3/esp32s3_oneshot.c
View file

@ -288,8 +288,8 @@ int esp32s3_oneshot_start(struct esp32s3_oneshot_s *oneshot,
/* Retrieve the duration from timespec in microsecond */
timeout_us = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
timeout_us = ts->tv_sec * USEC_PER_SEC +
(ts->tv_nsec / NSEC_PER_USEC);
/* Verify if it is a multiple of the configured resolution.
* In case it isn't, warn the user.
@ -459,7 +459,7 @@ int esp32s3_oneshot_current(struct esp32s3_oneshot_s *oneshot,
ESP32S3_TIM_GETCTR(oneshot->tim, usec);
*usec = *usec * (uint64_t)oneshot->resolution;
*usec = *usec * oneshot->resolution;
return OK;
}

4
arch/xtensa/src/esp32s3/esp32s3_tickless.c
View file

@ -430,8 +430,8 @@ int IRAM_ATTR up_timer_start(const struct timespec *ts)
up_timer_cancel(NULL);
}
cpu_ticks = SEC_2_CTICK((uint64_t)ts->tv_sec) +
NSEC_2_CTICK((uint64_t)ts->tv_nsec);
cpu_ticks = SEC_2_CTICK(ts->tv_sec) +
NSEC_2_CTICK(ts->tv_nsec);
tickless_setcounter(cpu_ticks);
g_timer_started = true;

2
arch/xtensa/src/esp32s3/esp32s3_tim_lowerhalf.c
View file

@ -410,7 +410,7 @@ static int timer_lh_settimeout(struct timer_lowerhalf_s *lower,
/* Set the timeout */
ESP32S3_TIM_SETALRVL(priv->tim, (uint64_t)timeout);
ESP32S3_TIM_SETALRVL(priv->tim, timeout);
return ret;
}

2
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
View file

@ -2253,7 +2253,7 @@ static void wifi_rtc_disable_iso(void)
int64_t esp32s3_timer_get_time(void)
{
return (int64_t)esp_hr_timer_time_us();
return esp_hr_timer_time_us();
}
/****************************************************************************

10
boards/arm/cxd56xx/drivers/audio/cxd56_audio_analog.c
View file

@ -65,8 +65,8 @@ static void set_mic_boot_time(void)
{
struct timespec start;
clock_systime_timespec(&start);
g_mic_boot_start_time = (uint64_t)start.tv_sec * 1000 +
(uint64_t)start.tv_nsec / 1000000;
g_mic_boot_start_time = start.tv_sec * 1000 +
start.tv_nsec / 1000000;
}
static void wait_mic_boot_finish(void)
@ -75,9 +75,9 @@ static void wait_mic_boot_finish(void)
{
struct timespec end;
clock_systime_timespec(&end);
uint64_t time = (uint64_t)end.tv_sec * 1000 +
(uint64_t)end.tv_nsec / 1000000 -
g_mic_boot_start_time;
uint64_t time = end.tv_sec * 1000 +
end.tv_nsec / 1000000 -
g_mic_boot_start_time;
if (time < CXD56_AUDIO_MIC_BOOT_WAIT)
{

1
boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/configs/nsh/defconfig
View file

@ -52,7 +52,6 @@ CONFIG_SYSLOG_PROCESSID=y
CONFIG_SYSLOG_PROCESS_NAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_UART0_BASE=0x9c090000

1
boards/arm/lc823450/lc823450-xgevk/configs/audio/defconfig
View file

@ -113,7 +113,6 @@ CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NXPLAYER=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TASKSET=y
CONFIG_SYSTEM_TIME64=y
CONFIG_SYSTEM_USBMSC=y
CONFIG_SYSTEM_USBMSC_DEVMINOR1=0
CONFIG_SYSTEM_USBMSC_DEVMINOR2=1

1
boards/arm/lc823450/lc823450-xgevk/configs/bt/defconfig
View file

@ -137,7 +137,6 @@ CONFIG_SYSTEM_NXPLAYER=y
CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TASKSET=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y

1
boards/arm/lc823450/lc823450-xgevk/configs/knsh/defconfig
View file

@ -103,7 +103,6 @@ CONFIG_START_MONTH=10
CONFIG_START_YEAR=2013
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_UART0_RXBUFSIZE=512
CONFIG_UART0_SERIAL_CONSOLE=y

1
boards/arm/lc823450/lc823450-xgevk/configs/kostest/defconfig
View file

@ -39,7 +39,6 @@ CONFIG_START_DAY=3
CONFIG_START_MONTH=10
CONFIG_START_YEAR=2013
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3
CONFIG_TESTING_OSTEST_STACKSIZE=2048

1
boards/arm/lc823450/lc823450-xgevk/configs/krndis/defconfig
View file

@ -161,7 +161,6 @@ CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NXPLAYER=y
CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_TESTING_OSTEST=y
CONFIG_UART0_RXBUFSIZE=512

1
boards/arm/lc823450/lc823450-xgevk/configs/nsh/defconfig
View file

@ -106,7 +106,6 @@ CONFIG_START_MONTH=10
CONFIG_START_YEAR=2013
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_SMP=y

1
boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig
View file

@ -161,7 +161,6 @@ CONFIG_SYSTEM_NXPLAYER=y
CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TASKSET=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y

1
boards/arm/lc823450/lc823450-xgevk/configs/usb/defconfig
View file

@ -109,7 +109,6 @@ CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TASKSET=y
CONFIG_SYSTEM_TIME64=y
CONFIG_SYSTEM_USBMSC=y
CONFIG_SYSTEM_USBMSC_DEVMINOR1=0
CONFIG_SYSTEM_USBMSC_DEVMINOR2=1

4
boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c
View file

@ -466,7 +466,7 @@ static int smps_start(struct smps_dev_s *dev)
{
pwrerr("ERROR: Can not achieve timc pwm "
"freq=%" PRIu32 " if fclk=%" PRIu64 "\n",
(uint32_t)TIMC_PWM_FREQ, (uint64_t)fclk);
(uint32_t)TIMC_PWM_FREQ, fclk);
ret = -EINVAL;
goto errout;
}
@ -483,7 +483,7 @@ static int smps_start(struct smps_dev_s *dev)
{
pwrerr("ERROR: Can not achieve timd pwm "
"freq=%" PRIu32 " if fclk=%" PRIu64 "\n",
(uint32_t)TIMD_PWM_FREQ, (uint64_t)fclk);
(uint32_t)TIMD_PWM_FREQ, fclk);
ret = -EINVAL;
goto errout;
}

1
boards/arm/stm32/nucleo-f302r8/configs/can/defconfig
View file

@ -50,6 +50,5 @@ CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

1
boards/arm/stm32/olimexino-stm32/configs/can/defconfig
View file

@ -92,7 +92,6 @@ CONFIG_STM32_TIM3_PARTIAL_REMAP=y
CONFIG_STM32_USART1=y
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=12
CONFIG_USART1_RXBUFSIZE=32
CONFIG_USART1_SERIAL_CONSOLE=y

1
boards/arm/stm32/olimexino-stm32/configs/composite/defconfig
View file

@ -116,7 +116,6 @@ CONFIG_STM32_USB=y
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_COMPOSITE=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=12
CONFIG_USART1_RXBUFSIZE=32
CONFIG_USART1_SERIAL_CONSOLE=y

1
boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig
View file

@ -104,7 +104,6 @@ CONFIG_STM32_USART1=y
CONFIG_STM32_USART2=y
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=12
CONFIG_USART1_RXBUFSIZE=32
CONFIG_USART1_SERIAL_CONSOLE=y

4
boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
View file

@ -447,7 +447,7 @@ static int smps_start(struct smps_dev_s *dev)
{
pwrerr("ERROR: Can not achieve tima pwm "
"freq=%" PRIu32 " if fclk=%" PRIu64 "\n",
(uint32_t)TIMA_PWM_FREQ, (uint64_t)fclk);
(uint32_t)TIMA_PWM_FREQ, fclk);
ret = -EINVAL;
goto errout;
}
@ -464,7 +464,7 @@ static int smps_start(struct smps_dev_s *dev)
{
pwrerr("ERROR: Can not achieve timb pwm "
"freq=%" PRIu32 " if fclk=%" PRIu64 "\n",
(uint32_t)TIMB_PWM_FREQ, (uint64_t)fclk);
(uint32_t)TIMB_PWM_FREQ, fclk);
ret = -EINVAL;
goto errout;
}

1
boards/arm/stm32/stm32f4discovery/configs/canard/defconfig
View file

@ -47,7 +47,6 @@ CONFIG_STM32_PWR=y
CONFIG_STM32_SPI1=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_TIME64=y
CONFIG_USART2_RXBUFSIZE=128
CONFIG_USART2_SERIAL_CONSOLE=y
CONFIG_USART2_TXBUFSIZE=128

1
boards/arm64/a527/avaota-a1/configs/nsh/defconfig
View file

@ -100,7 +100,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_PROGNAME="init"
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_FPUTESTDISABLE=y

1
boards/arm64/a64/pinephone/configs/lcd/defconfig
View file

@ -56,7 +56,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_UART0_SERIAL_CONSOLE=y

1
boards/arm64/a64/pinephone/configs/lvgl/defconfig
View file

@ -74,7 +74,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_UART0_SERIAL_CONSOLE=y

1
boards/arm64/a64/pinephone/configs/nsh/defconfig
View file

@ -55,7 +55,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_UART0_SERIAL_CONSOLE=y

1
boards/arm64/a64/pinephone/configs/sensor/defconfig
View file

@ -60,7 +60,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_UART0_SERIAL_CONSOLE=y

1
boards/arm64/bcm2711/raspberrypi-4b/configs/cgol/defconfig
View file

@ -57,7 +57,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_OSTEST=y
CONFIG_USEC_PER_TICK=1000
CONFIG_USERLED=y

1
boards/arm64/bcm2711/raspberrypi-4b/configs/coremark/defconfig
View file

@ -50,6 +50,5 @@ CONFIG_START_MONTH=11
CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_READLINE=y
CONFIG_SYSTEM_TIME64=y
CONFIG_USEC_PER_TICK=1000
CONFIG_USERLED=y

1
boards/arm64/bcm2711/raspberrypi-4b/configs/fb/defconfig
View file

@ -52,7 +52,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_OSTEST=y
CONFIG_USEC_PER_TICK=1000
CONFIG_USERLED=y

1
boards/arm64/bcm2711/raspberrypi-4b/configs/lvgl/defconfig
View file

@ -61,7 +61,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_USEC_PER_TICK=1000
CONFIG_USERLED=y
CONFIG_VIDEO_FB=y

1
boards/arm64/bcm2711/raspberrypi-4b/configs/nsh/defconfig
View file

@ -53,7 +53,6 @@ CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_USEC_PER_TICK=1000

1
boards/arm64/bcm2711/raspberrypi-4b/configs/ostest/defconfig
View file

@ -49,7 +49,6 @@ CONFIG_START_MONTH=11
CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_READLINE=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_LOOPS=5
CONFIG_USEC_PER_TICK=1000

1
boards/arm64/bcm2711/raspberrypi-4b/configs/sd/defconfig
View file

@ -70,7 +70,6 @@ CONFIG_SYSLOG_INTBUFFER=y
CONFIG_SYSLOG_TIMESTAMP=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_SD_STRESS=y

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