mirror of
https://github.com/apache/nuttx.git
synced 2026-08-22 14:08:30 +00:00
8770fbea0f
Adds a driver for the external QSPI PSRAM hanging off QMI chip select 1, such as the 8 MiB APS6404 fitted on the Pimoroni Pico Plus 2. rp23xx_psramconfig() assigns the CS1 pin, reads the device ID over the QMI direct interface to confirm an APS6404-family part (KGD 0x5D), resets it into quad mode and programs the QMI M1 timing/read/write formats so the region at 0x11000000 becomes directly addressable and writable. Because driving the QMI in direct mode stalls execute-in-place from the flash, the detection and (re)configuration code runs from RAM (.time_critical) with interrupts disabled; the command bytes are selected with immediates rather than a .rodata table for the same reason. The register values follow the Raspberry Pi Pico SDK setup_psram(). The detection routine only keeps the QMI DIRECT_CSR synchronization that is strictly necessary. Each candidate busy-wait was removed one at a time and re-verified on hardware: the post-enable "cooldown" waits, the READ_ID TXEMPTY wait (redundant with the BUSY wait after it), and a fixed nop delay proved unnecessary and are omitted. The three BUSY waits that remain -- after the quad-mode nudge, after each READ_ID byte, and after each reset/quad-enable command -- are required and carry a comment explaining that the frame must finish shifting before the chip select is deasserted, and what breaks otherwise (garbage ID reads, or the shared QMI bus wedging). rp23xx_psram_restore() re-applies the M1 configuration and is meant to be called from the flash write path, which goes through the bootrom and reconfigures the shared QMI for chip select 0. rp23xx_heaps.c is wired into the build and now uses the detected size, so the PSRAM is exposed to the memory manager (added to the main heap, used as a separate heap, or as the user heap) and is skipped cleanly when no PSRAM is present. Enabled by default on the pimoroni-pico-2-plus:nsh configuration, where it adds the 8 MiB to the main heap. A documentation page for the Pimoroni Pico Plus 2 is added alongside the other rp23xx boards, covering its serial console, LED, the external PSRAM and how it is exposed to the heap, the supported capabilities and the available configurations, with a photo of the board. Tested on Pimoroni Pico Plus 2 hardware: detection reports the 8 MiB APS6404, the region is read/write across its whole range (ramtest word, half-word and byte passes, marching/pattern/address-in-address), and the heap reports the extra 8 MiB. Assisted-by: Claude Code:claude-opus-4-8 Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com> |
||
|---|---|---|
| .. | ||
| a1x | ||
| am67 | ||
| am335x | ||
| at32 | ||
| bcm2708 | ||
| c5471 | ||
| cxd56xx | ||
| dm320 | ||
| efm32 | ||
| eoss3 | ||
| fvp-v8r-aarch32 | ||
| gd32f4 | ||
| goldfish | ||
| ht32f491x3 | ||
| imx1 | ||
| imx6 | ||
| imx9 | ||
| imxrt | ||
| kinetis | ||
| kl | ||
| lc823450 | ||
| lpc17xx | ||
| lpc31xx | ||
| lpc40xx | ||
| lpc43xx | ||
| lpc54xx | ||
| lpc214x | ||
| lpc2378 | ||
| max326xx | ||
| moxart | ||
| mps | ||
| mx8mp | ||
| nrf52 | ||
| nrf53 | ||
| nrf91 | ||
| nuc1xx | ||
| phy62xx | ||
| qemu | ||
| ra4m1 | ||
| rp23xx | ||
| rp2040 | ||
| rtl8720f | ||
| rtl8721dx | ||
| s32k1xx | ||
| s32k3xx | ||
| sam34 | ||
| sama5 | ||
| samd2l2 | ||
| samd5e5 | ||
| samv7 | ||
| stm32c0 | ||
| stm32f0 | ||
| stm32f1 | ||
| stm32f2 | ||
| stm32f3 | ||
| stm32f4 | ||
| stm32f7 | ||
| stm32g0 | ||
| stm32g4 | ||
| stm32h5 | ||
| stm32h7 | ||
| stm32l0 | ||
| stm32l1 | ||
| stm32l4 | ||
| stm32l5 | ||
| stm32n6 | ||
| stm32u5 | ||
| stm32wb | ||
| stm32wl5 | ||
| str71x | ||
| tiva | ||
| tms570 | ||
| xmc4 | ||
| index.rst | ||