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The specific Cortex-R52 implementation could be configured with a Single-Precision-only FPU (SP-only) and no Neon unit. Executing double-precision instructions (e.g., `vadd.f64`) triggers an Undefined Instruction exception. The standard `-mfpu=fp-armv8` implicitly enables double-precision, which is unsafe for this hardware. `-mfpu=fpv5-sp-d16` is selected as the closest architectural match. - It enforces Single Precision code generation (preventing crashes). - It enables VFPv4/FPv5 features like FMA (Fused Multiply-Add) supported by the CR52 FPU. - It restricts the register set to d0-d15, matching the hardware constraints. This ensures the compiler utilizes hardware FPU and FMA acceleration without emitting illegal double-precision instructions. Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||