Commit graph

24418 commits

Author SHA1 Message Date
Lup Yuen Lee
ebc75b0ed5 arch/tricore: Fix --help-- in Kconfig
This PR fixes a typo at `--help--` that causes NuttX Builds to fail, it should have been `---help---`. This is a recurring problem, NuttX CI uses a different way of handling NuttX Configs (it doesn't use `tools/configure.sh`)

https://github.com/lupyuen/nuttx-riscv64/actions/runs/22929878852/job/66548808341#step:5:161
```
$ tools/configure.sh rv-virt:nsh
arch/tricore/Kconfig:124: syntax error
arch/tricore/Kconfig:123: unknown option "--help--"
arch/tricore/Kconfig:124:warning: ignoring unsupported character ','
arch/tricore/Kconfig:124: unknown option "In"
```

Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
2026-03-11 13:06:13 +08:00
simbit18
a64047ec1c arch/arm/src/max326xx: CMake build implemented for MAX326xx Series
- added MAX326xx Series

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-03-10 17:26:42 -04:00
zhangyu117
72be575b1a arch/tricore: support tc4evb board.
add new chip named tc4xx and board tc4evb

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
4be3075a5c arch/tricore: change heap symbol to support multi config
Let the linker script decide the location of the heap.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
5349a0ebc0 tricore/cmake: change tc3xx.cmake to chip.cmake
rename tc3xx.cmake to chip.cmake

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyu117
5b18435f96 arch/tricore: Adjust the related structures of arch and chip.
support tc4evb board, so need adjust some Kconfig

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyu117
c98eccf08d arch/tricore: adjust arch-related irq.h
tc3 and tc4 use common irq.h

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
cb161c2ae3 arch/tricore: include arch.h in irq.h
add arch.h in irq.h

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
22db8fbc71 arch/tricore: fixed cxx build issue
perform type conversion to eliminate warnings

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
Tiago Medicci Serrano
cda4af9f00 arch/risc-v/espressif/esp32p4: Support ESP32-P4 on NuttX
This commit adds support for the Espressif's RISC-V-based ESP32-P4
chip along with its ESP32-P4-Function-EV-Board board.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-03-09 21:40:25 +01:00
Saurav Pal
8ddcf81484 boards/arm64/bcm2711/raspberrypi-4b: Fix GPIO
* Fix GPIO unspecified behavior on some GPIO ports.
* Fix GPIO undefined behavior caused by uncleared set or reset bits.

Signed-off-by: Saurav Pal <resyfer.dev@gmail.com>
2026-03-08 14:30:40 -04:00
Pavel Pisa
fad037e4ca stm32h7: add configuration for STM32H723 chips (STM32H723ZG and STM32H723VG)
Add definition to setup appropriate reduced SRAM sizes
CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX.
The define should make addition of other STM32H72X
and TM32H73X chips easier.

Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
2026-03-05 16:51:49 -03:00
Pavel Pisa
f2ecb8b6e9 stm32h7: increase IRQ count to support stm32h723zg
Increase IRQ count and add irqinfo handling in order to support
the stm32h723zg chip.

Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
2026-03-05 16:51:49 -03:00
Aditya Yadav
574fc64ab9 sim: Fix linker support and macOS host build issues
Update SIM configuration and CMake toolchain to resolve
linker errors when building on macOS. Adjust POSIX host
implementation to ensure successful compilation and
proper behavior of the sim target.

Modified:
- arch/sim/Kconfig
- arch/sim/src/cmake/Toolchain.cmake
- arch/sim/src/sim/posix/sim_hostmisc.c

Signed-off-by: Aditya Yadav <166515021+aditya0yadav@users.noreply.github.com>
2026-03-05 21:52:58 +08:00
Jari Nippula
5cd57fa27e arch/arm64: handle fatal user exception
Print user exception reason class and description
Print register dump

Signed-off-by: Jari Nippula <jari.nippula@tii.ae>
2026-03-05 20:30:09 +08:00
Michal Lenc
b3656d34b6 arch/arm/src/samX/sam_gpioirq.c: fix pin base address calculation
GPIO PIN base address calculation had double right shift, thus call
to SAM_PION_BASE was always with port = 0 instead of correct port
number. As a result, function sam_gpioirq didn't correctly configure
additional interrupt modes (only rising or falling edge and level
interrupts).

The issue occured on SAMv7 and SAM34 platforms (likely copy-pasted
from one to another).

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2026-03-05 12:41:43 +08:00
Tiago Medicci Serrano
d2c85a9fa0 arch/risc-v/espressif: Update common-source integration for RISC-V devices
This commit updates the common-source integration for RISC-V-based
Espressif devices (ESP32-C3, ESP32-C6, and ESP32-H2). This is part of a
larger common-source update split by architecture for better maintainability
of the already-supported devices and upcoming devices.

Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- Board defconfigs for all RISC-V Espressif boards
- Critical section handling improvements

Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
  options from interrupt sources to CPU interrupts, providing flexibility
  required by modern peripherals. Although this introduces breaking changes
  to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
  Kconfig option is explicitly checked during startup to ensure proper
  configuration. This validation prevents runtime issues from configuration
  mismatches.

Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.

Tested configurations:
- All defconfigs were built and tested, inclusing `ostest`.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>

To be merged with RISC-V implementation
2026-03-05 12:41:14 +08:00
Kerogit
b0af360212 arch/avr/src/avrdx: fixed typo in avrdx_gpio_isr_mux.c
This patch fixes a typo in a comment. (Tested: checkpatch - all checks
pass, compilation yields binary with identical SHA256 checksum
with and without the patch.)

Signed-off-by: Kerogit <kr.git@kerogit.eu>
2026-02-28 20:59:01 -05:00
Maarten Zanders
f70d40bca7 arch/arm/imx9: add i.MX93 Cortex-M33 support.
Add hardware register headers and driver support for the NXP i.MX93
Cortex-M33 core. All new and modified code is guarded by
ARCH_CHIP_IMX93_M33 preprocessor defines; existing i.MX95-M7 builds
are unaffected.

New drivers:
- imx9_xcache.c - off core cache init and maintenance
- imx9_ccm.c - generic CCM abstraction layer

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-28 10:30:06 +08:00
Maarten Zanders
461e7bd91f arch/arm/imx9: Kconfig: remove redundant menu wrapper around chip selection.
The menu and choice had the same purpose; keep only the choice.

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-28 10:30:06 +08:00
Maarten Zanders
a82293e3ef arch/arm/imx9: make MU driver generic for all i.MX9 variants.
Rename imx95_mu_* functions to imx9_mu_*, decoupling the MU driver
API from the iMX95-specific naming in preparation for iMX93-M33
support.

Add ARCH_CHIP_IMX95_M7 dependency to the MU instance Kconfig entries
so they are only visible for the appropriate target.

Switch imx9_mu.c to include the generic imx9_memorymap.h instead of
the imx95-specific header.

Fix incorrect help text for MU8 (was copy-pasted from MU5).

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-28 10:30:06 +08:00
Maarten Zanders
7ee57f42bb arch/arm/imx9: rptun/rsctable: move addresses and MU instance to headers.
Extract chip-specific constants from imx9_rptun.c and imx9_rsctable.c
into new dispatch headers:

- hardware/imx9_rsctable.h: VDEV0_VRING_BASE and RESOURCE_TABLE_BASE,
  selected per ARCH_CHIP define
- hardware/imx9_rptun.h: MU_INSTANCE, selected per ARCH_CHIP define

Rename the misnamed VRING_SHMEM constant in imx9_rptun.c to
RESOURCE_TABLE_BASE, which correctly reflects that this address points
to the resource table, not the vring shared memory region.

No functional change for i.MX95-M7 builds.

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-28 10:30:06 +08:00
Maarten Zanders
3631256219 arch/arm/imx9: irq: replace hardcoded NVIC register lists with loops.
Use NVIC_IRQ_ENABLE(n) and NVIC_IRQ_PRIORITY(n) macros in
imx9_dumpnvic() to iterate over all NVIC registers programmatically
based on CONFIG_ARCH_NINTS (IMX9_IRQ_NEXTINT), rather than
enumerating named per-range register defines. Output is grouped
4-per-line for priority and 4-per-line for enable registers,
matching the original layout.
This avoids accessing registers which don't exist when extending
the interrupt count.

Also replace named NVIC_IRQxx_yy_ENABLE constants in imx9_irqinfo()
with NVIC_IRQ_ENABLE(n), avoiding naming conflicts between chips
with different IRQ counts.

Fix the upper boundary in the >192 IRQ branch from 219 to 224 to
align with the 32-interrupt register granularity.

Change %08x to %08lx to silence warnings from the compiler for
the debug dump.

No functional change for existing i.MX95-M7 builds.

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-28 10:30:06 +08:00
Maarten Zanders
2c5ffacff5 arch/arm/imx9: iomuxc: introduce IOMUXC_MUX_CTL_GPIO_LASTIO_OFFSET.
The GPIO mux range check in imx9_iomux_gpio() used a hardcoded
IOMUXC_MUX_CTL_GPIO_IO37_OFFSET as the upper bound, which is
i.MX95-specific. Move the define to imx95_iomuxc.h as an alias of
the last GPIO_IO entry, and use the named constant in the comparison.

No functional change; i.MX95 builds are unaffected.

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-28 10:30:06 +08:00
Maarten Zanders
6f859b56c7 arch/arm/imx9: clockconfig: preparatory cleanup for i.MX93 support.
- Guard imx9_gpc.h inclusion with CONFIG_IMX9_WFI_AWAKES_AT_SYSTICK
  to avoid a GPC dependency on chips that lack GPC
- Add depends on ARCH_CHIP_IMX95_M7 to IMX9_WFI_AWAKES_AT_SYSTICK
  since GPC wake configuration is i.MX95-specific
- Move XTAL_FREQ and ROOT_CLOCK_OFFSET defines to imx95_clock.h
- Make imx9_sm_setrootclock() and imx9_sm_getipfreq() static;
  they are not referenced outside this translation unit

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-28 10:30:06 +08:00
simbit18
84a512759d arch/arm/src/sama5: CMake build implemented for Microchip's SAMA5 Family
- added Microchip's SAMA5 Family

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-02-27 16:33:00 -05:00
taoliu
e3b1e5914e arch/arm/src: Add necessary conversion between tick and usec for tickless
When testing tickless scheme with default arm_systick.c, we found the
count writed to systick register is too smaller the expected, just the
ticks not count, and os runing abnormally with too much interrupter.
Add necessary coversion, then system run well.

Signed-off-by: taoliu <taoliu@asrmicro.com>
2026-02-27 14:08:51 +01:00
zhenwei fang
f0fc695a81 arch/sim: fix warning ‘sim_buttonmap’ defined but not used
N/A

Signed-off-by: zhenwei fang <fangzhenwei@bytedance.com>
Signed-off-by: chao an <anchao.archer@bytedance.com>
2026-02-27 19:54:46 +08:00
xingrentai.1
bf83ff3fbd arch/sim: guard X11 touchscreen events with CONFIG_SIM_TOUCHSCREEN
The X11 event loop in the POSIX simulator was processing MotionNotify
(touch/mouse movement)and ButtonPress/ButtonRelease events unconditionally,
even when the touchscreen feature(CONFIG_SIM_TOUCHSCREEN) was disabled.

This could lead to unnecessary event processing, potential compiler warnings
about unusedfunctions (e.g., sim_buttonevent), or unintended behavior in simulator
builds withouttouchscreen support. The touchscreen-related event handling should
only be active whenthe corresponding configuration is enabled.

This fix wraps the MotionNotify and ButtonPress/ButtonRelease event handling
logicwith #ifdef CONFIG_SIM_TOUCHSCREEN guards to:

1. Ensure touchscreen/mouse event processing is only compiled when CONFIG_SIM_TOUCHSCREEN is enabled.
2. Eliminate unused code warnings in non-touchscreen simulator builds.
3. Align event loop behavior with the configured feature set, reducing unnecessary runtime overhead.

The change maintains full touchscreen functionality when the config is enabled, whilecleaning up the
code path for builds that don't require touchscreen support.

Signed-off-by: chao an <anchao.archer@bytedance.com>
2026-02-27 19:54:46 +08:00
xingrentai.1
ee3e931812 arch/sim: fix X11 framebuffer window not visible in POSIX simulator
The X11 framebuffer implementation in the POSIX simulator was creating a window
and graphics context but failing to map (display) the window to thescreen with XMapWindow().

This omission meant the framebuffer window would be created in the X11server but remain hidden,
making it impossible to see any graphics outputfrom the simulator. The window existed in the X11
server's state but wasnot rendered to the screen.

This fix adds the missing XMapWindow(display, g_window) call aftercreating the graphics context, which:
1. Maps the created X11 window to the screen (makes it visible).
2. Ensures framebuffer output is rendered to the display as expected.
3. Maintains compatibility with existing X11 framebuffer logic.

The change restores basic visibility of the simulator's framebuffer window,
fixing a critical usability issue for graphics-related testing in the POSIX simulator.

Signed-off-by: chao an <anchao.archer@bytedance.com>
2026-02-27 19:54:46 +08:00
Tiago Medicci Serrano
18be6955c6 arch/xtensa/src/common: Create SoC-specific initialization routine
This commits adds a function that can be implemented by any vendor
to allow SoC-specific functions to be called by `up_initialize`.
Please note that `up_initialize` is provided by the arch level, but
it doesn't allow SoC-specific initialization. Although it could be
possible to run such initialization on board-level, semantically
it isn't related to the board, but with the SoC. As an example of
such implementation, some SoCs require RTC subsystem initialization
to occur before the OS is completely initialized.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 08:12:19 -03:00
Tiago Medicci Serrano
ba20c930f8 arch/risc-v/src/common: Create SoC-specific initialization routine
This commits adds a function that can be implemented by any vendor
to allow SoC-specific functions to be called by `up_initialize`.
Please note that `up_initialize` is provided by the arch level, but
it doesn't allow SoC-specific initialization. Although it could be
possible to run such initialization on board-level, semantically
it isn't related to the board, but with the SoC. As an example of
such implementation, some SoCs require RTC subsystem initialization
to occur before the OS is completely initialized.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 08:12:19 -03:00
Chip L.
6cb6c45987 arch/xtensa/esp32: Fix buffer overflow in SPI poll exchange
The esp32_spi_poll_exchange() function previously used a hardcoded
length of sizeof(uint32_t) (4 bytes) for memcpy() operations and
pointer increments, disregarding the actual remaining transfer_size.

When an SPI transaction involved a data length not aligned to 4 bytes
(such as a 1-byte payload commonly used in sub-GHz radio drivers),
the driver forced a 4-byte memory transfer. This caused out-of-bounds
reads and writes, leading to stack smashing and fatal CPU exceptions
(e.g., EXCCAUSE=0000).

This patch resolves the memory corruption vulnerability by:
1. Calculating a precise `chunk` size for each iteration, strictly
   bounded by the remaining `transfer_size`.
2. Limiting the memcpy() operations and the subsequent pointer
   increments (tp and rp) to this exact chunk size.
3. Zero-initializing the temporary TX register (w_wd) before copying
   to clear padding and prevent reading uninitialized memory.
4. Adding a NULL check for the receive pointer (rp) prior to the
   memcpy operation to prevent unintended memory writes.

Signed-off-by: Chip L. <chplee@gmail.com>
2026-02-27 08:10:46 -03:00
fangzhenwei
e4ed6156ca arch/sim: fix incomplete HCI socket data reading in simulator interrupt handler
The sim_bthcisock_interrupt() handler for Bluetooth HCI sockets in the simulatorwas using
an if statement to check for available data on the HCI socket. Thismeant that only a single
packet would be read and processed per interrupt trigger,even if multiple packets were waiting
in the socket buffer.

This led to incomplete data processing: unread packets would remain in the bufferuntil the next
interrupt tick, causing delayed handling of Bluetooth HCI events/commands,packet backlogs,
or missed data in high-throughput scenarios.

This fix replaces the if with a while loop to:

1. Continuously check for and read available data from the HCI socket until no more
   packets are present in the buffer.
2. Ensure all pending HCI packets are processed in a single interrupt handler invocation.
3. Eliminate packet backlogs and reduce latency in Bluetooth HCI communication.

The change maintains the same core data reception logic (bthcisock_receive()) butensures it runs
for all available packets, improving the reliability and responsivenessof the simulator's Bluetooth HCI socket implementation.

Signed-off-by: chao an <anchao.archer@bytedance.com>
2026-02-26 08:15:28 -03:00
yinshengkai
e62e245f64 arm64/cmake: fix typo in CMAKE_STRIP flag
Typo in CMAKE_STRIP option (strl dunneeded -> strip-unneeded).

Signed-off-by: yinshengkai <yinshengkai@bytedance.com>
2026-02-26 12:12:35 +01:00
simbit18
49b2e7d6a6 arch/arm/src/stm32wl5: CMake build implemented for STM32 STM32WL5
- added STMicroelectronics STM32WL5

Signed-off-by: simbit18 <simbit18@gmail.com>

Update CMakeLists.txt

Update CMakeLists.txt
2026-02-26 06:20:41 +08:00
Matteo Golin
2d768c294e arch/delays: Invalid default value for BOARD_LOOPSPERMSEC
Changes the default value for CONFIG_BOARD_LOOPSPERMSEC to -1, which is
invalid. All boards that forget to configure this value will encounter a
static assertion at compile time, enforcing that configurations
upstreamed to NuttX have calibrated values for correct delay timings.

Boards which implement ALARM_ARCH or TIMER_ARCH do not rely on the
busy-loop delay implementation and thus only have a run-time check to
ensure proper delay-timings (in the case where delays are used before
the alarm/timer driver is registered).

Some boards already in the NuttX upstream do not have calibrated values,
but there are no users who currently own the board to submit a
calibrated value for the configurations to use. In this scenario, the
value is temporarily set to 0 and a warning is displayed so that users
of these boards are informed of the calibration process.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2026-02-25 15:00:03 -03:00
simbit18
6f92e14e81 arch/arm/src/a1x: CMake build implemented for Quicklogic EOS S3
- added Quicklogic EOS S3

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-02-25 06:47:58 +08:00
simbit18
c6c9876227 arch/arm/src/a1x: CMake build implemented for Allwinner A1X family
- added Allwinner A1X family

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-02-24 21:40:48 +08:00
Eren Terzioglu
90147a72c2 arch/xtensa/espressif: Fix SHA errors
Fix SHA errors for esp32[-s2|-s3]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2026-02-24 12:57:46 +01:00
Eren Terzioglu
19b6e15dbd arch/risc-v/espressif: Fix SHA errors
Fix SHA errors for esp32[-c3|-c6|-h2]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2026-02-24 12:57:46 +01:00
Vlad Pruteanu
4775f5ba21 xtensa/esp32: Fix HMAC-SHA when a long key is used
When using a key that is longer than the block size of the hashing
algorithm used, the key must be hashed before it is used.

Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
2026-02-24 08:32:19 -03:00
simbit18
6b621999d9 arch/arm/src/stm32l5: CMake build implemented for STM32 STM32L5 Series
- added STM32 STM32L5 Series

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-02-23 22:12:48 +08:00
Maarten Zanders
65207ae1c5 serial/uart_rpmsg: add _raw version of driver
Mainline Linux doesn't use data encapsuation or flow control in its
tty_rpmsg driver. Create a NuttX counterpart which matches this
implementation.
This driver uses the static "rpmsg-tty" name to connect with the
remote service.

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-23 09:19:57 -03:00
Ari Kimari
966be68259 arch/imx9/enet: Add MII clock calculation
Add MII clock calculation from root clock
Remove MII clock divider define

Signed-off-by: Ari Kimari <ari.kimari@tii.ae>
2026-02-21 07:51:44 +08:00
simbit18
12d4f385bd arch/arm/src/stm32wb: CMake build implemented for STM32 STM32WB Series
- added STM32 STM32WB Series

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-02-21 07:25:40 +08:00
Maarten Zanders
643f33934e arch/arm: remove all "select ARMV8M_HAVE_STACKCHECK".
Stack checking is not optional on armv8m. This config
option does not exist.

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-20 13:17:22 -05:00
Filipe Cavalcanti
293d33f5dd arch/xtensa/esp32: select I2C_DRIVER on I2C
Automatically select I2C_DRIVER when ESP32_I2C is selected.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2026-02-20 14:56:54 +01:00
simbit18
53fd998502 arch/arm/src/samd5e5: CMake build implemented for Microchip's SAM D5x/E5x Family
- added Microchip's SAM D5x/E5x Family

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-02-19 15:08:42 -03:00
Atsunori Saito
fc1ae9b7be imxrt/lpspi: Fix correct LPSPI DMA transfer size for 16-bit
- Fix byte count calculation for 16-bit SPI words
  using shift-by-1 instead of shift-by-2
- Use word count instead of byte count for DMA
  iteration config on both RX and TX channels

Signed-off-by: Atsunori Saito <sai@yedo.com>
2026-02-18 09:19:22 -03:00