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3631256219
Use NVIC_IRQ_ENABLE(n) and NVIC_IRQ_PRIORITY(n) macros in imx9_dumpnvic() to iterate over all NVIC registers programmatically based on CONFIG_ARCH_NINTS (IMX9_IRQ_NEXTINT), rather than enumerating named per-range register defines. Output is grouped 4-per-line for priority and 4-per-line for enable registers, matching the original layout. This avoids accessing registers which don't exist when extending the interrupt count. Also replace named NVIC_IRQxx_yy_ENABLE constants in imx9_irqinfo() with NVIC_IRQ_ENABLE(n), avoiding naming conflicts between chips with different IRQ counts. Fix the upper boundary in the >192 IRQ branch from 219 to 224 to align with the 32-interrupt register granularity. Change %08x to %08lx to silence warnings from the compiler for the debug dump. No functional change for existing i.MX95-M7 builds. Signed-off-by: Maarten Zanders <maarten@zanders.be> |
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| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
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| tricore | ||
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| CMakeLists.txt | ||
| Kconfig | ||