Fix Espressif timer registering ID. Espressif's general purpose
timers are grouped in different Timer Groups, which may contain
more than one general purpose timer. The current implementation is
related to the timer groups (timer0 refers to Timer Group 0, for
instance), but previous registering method was referring to the
timer inside each group, which caused it to fail when more than
one timer group was being selected because only the first timer
on each group is being actually registered.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Always clear the BSS section before calling `bootloader_init`.
This is necessary because, otherwise, `bootloader_init` may fail
even before `bootloader_clear_bss_section` is called again by that
function.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Commit an initial blank frame during goldfish_gpu_fb_register() to
avoid rendering a stale frame from the emulator after reboot.
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
Critical sections only disable interrupts on the local CPU, which
is insufficient for SMP. Replace with per-device spinlocks to
ensure proper mutual exclusion across all cores.
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
Implement hardware breakpoint and watchpoint support for TriCore
architecture using the Trigger Event (TREVT) registers. This enables
the standard NuttX debugpoint API (up_debugpoint_add/remove) on TriCore
processors, supporting read/write/execute watchpoints and breakpoints
via the on-chip debug unit.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
The Ethernet MAC (57.11.4) was already configured in the code,
but it was necessary to configure the Transmit Descriptor (57.10.3)
in read format:
- Checksum Interface Control for IP, payload and pseudo-header
Add checks for Recceive Descriptor (57.10.4) in read format:
- Receive Descriptor 1 is valid from Receive Descriptor 3
- IP checksum was not bypassed
- IP header checksum error op IP payload checkerror is set
Testing with STM32 Nucleo-144 using iperf, improved transmission from
35 MBits/s to 50MBits/s.
Signed-off-by: Patrick José Pereira <patrickelectric@gmail.com>
Add support for the i.MX9 SAR ADC block.
Based on the arm64 version but slightly different init due to SCMI and
different channel mask for i.MX95.
The driver provides initialization, deinitialization, channel-mask
validation, and one-shot reads for the supported ADC channels. It also
handles the ADC clock bring-up, power-up sequence, calibration, and raw
12-bit result extraction from the per-channel data registers.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Increase MM_REGIONS from 5 to 6 to accomodate latest changes from
initialization refactor.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Fix an issue where button presses were missed in the touchscreen
example due to incorrect packet processing.
Previously, the driver waited to accumulate a batch of packets but only
processed the first one, effectively discarding the rest. The driver
now reads and processes packets one at a time to ensure no input
events are lost.
Also fixed typo: usbhost_xythreshold does not exist.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Align the uORB application documentation with the actual command names, source layout, and configuration options in apps/system/uorb.
This updates the page to describe both uorb_listener and uorb_generator, uses the registered NSH command names in usage examples, and documents the listener and generator options to match the current implementation.
It also adds the relevant Kconfig enablement notes so the documented commands are easier to find and use.
Tested with:
- make html SPHINXOPTS="-W" -j
Signed-off-by: hanzhijian <hanzhijian@zepp.com>
1. The original method of restoring the register context relies on
the ret instruction, which does not conform to the semantics of
longjmp not returning.
2. There are csa leak during longjmp and need recycle.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Add setjmp/longjmp support for TriCore architecture using iLLD
intrinsics to save and restore the CSA (Context Save Area) chain.
This implementation saves upper/lower context registers and walks
the CSA linked list to restore the full call context on longjmp.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
Pass -no-pie through the gcc driver instead of forwarding it as -Wl,-no-pie.
On Ubuntu 20 with GCC 9, sim:nsh failed during the final link step with /usr/bin/ld: cannot find -lgcc_s.
This change fixes the link failure in that environment.
Signed-off-by: hanzhijian <hanzhijian@zepp.com>
Resolve PLT entries at load time on Linux hosts so early host calls do not enter the lazy binder with simulated interrupts masked.
On Ubuntu 20 with GCC 9, the sim:nsh binary linked successfully after the -no-pie fix but crashed very early at runtime inside _dl_fixup / _dl_runtime_resolve_xsavec when up_irq_save() triggered a first-time PLT resolution.
Setting LD_BIND_NOW=1 avoided the crash and allowed NSH to start, which showed lazy binding was the trigger.
Signed-off-by: hanzhijian <hanzhijian@zepp.com>
1. Make tricore_backtrace.c conditional on CONFIG_SCHED_BACKTRACE,
consistent with RISC-V and ARM architectures.
2. Add NULL return address check to terminate early on invalid entries.
3. Fix non-current task backtrace to use regs[REG_LPCXI] which
preserves the UL bit needed for correct CSA type identification.
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
up_fpucmp was comparing lower CSA registers (offset 0) using upper CSA
register definitions (REG_D8-D15). Since up_saveusercontext stores:
- Lower CSA at saveregs[0..15]
- Upper CSA at saveregs[16..31]
The fix adds TC_CONTEXT_REGS offset to point to the upper CSA and
compares only D8-D15 which are the FPU data registers on TriCore.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Implement up_fpucmp to compare FPU register state between two
saved contexts. This is used by the ostest FPU test to verify
that FPU registers are properly preserved across context switches.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Initialize the FPU and enable the FZ (flush-to-zero) trap for
TriCore TC4xx processors. This ensures floating-point divide-by-zero
exceptions are properly caught and reported via the trap handler.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
for tc3xx, without div64 hw inst:
gcc toolchain software way: 684ns
tasking toolchain software way: 3516ns.
invdiv_u64: 182ns
for tc4xx, with div64 hw inst:
div64 hw inst cost 182ns.
invdiv_u64: 125ns
Although there is a delay of tens of nanoseconds for tc4xx, the impact
on performance is minimal, but for simplicity, invdiv_u64 is used.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Add performance counter support for TriCore architecture using the
CPU clock counter (CCNT). Implements up_perf_init, up_perf_getfreq,
up_perf_gettime and up_perf_convert interfaces.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
nxsched_waitpid is only available when CONFIG_SCHED_WAITPID is
enabled. Wrap the call with #ifdef to fix the build error when
this option is disabled.
Signed-off-by: huojianchao <huojianchao@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Replace C11 atomic types and operations with NuttX native atomic
interfaces (atomic_t, atomic_set, atomic_fetch_and_acquire,
atomic_fetch_or_acquire) to avoid build failures on toolchains
that lack full C11 atomics support.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
MX25L12873G is a SPI memory very similar to MX25L25673G,
but 128Mbit, which means it does not use 4-byte addresses.
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
Adds a build_path argument for when CMake builds are used.
This solves a problem when building the nxdiag tool with CMake.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Include i.MXRT1170 as supported chip and add newer unsupported chips.
Also updated the cache chapter to reflect current state of driver and
support.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Ensure esp-hal copied headers are generated during nuttx_context so parallel CMake builds cannot compile sources before arch/chip/irq.h exists.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Implement up_backtrace() for TriCore by walking the CSA chain and
collecting return addresses from upper CSA A11 register.
Signed-off-by: LukeKun <donghaokun@lixiang.com>
Update the destination register to r15 (PC) for test and clean
operations, as specified by the ARM926EJ-S Technical Reference
Manual (TRM). Using the wrong destination register prevented the
loop condition from updating correctly, resulting in an infinite
loop.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
- Invoke `codesign` and after lief rewrites the binary, so the modified
Mach-O remains loadable on macOS.
- Run the patch script via a dedicated `sim_patch_macho_initsection`
custom target attached to `nuttx_post`, instead of a POST_BUILD
command on the `nuttx` target.
Signed-off-by: Shoji Tokunaga <toku@mac.com>
The sim architecture needs to defer C++ global constructors until after
NuttX kernel initialization completes. On macOS this was previously done
via a runtime hack (sim_macho_init.c): a __attribute__((constructor))
function intercepted constructors, saved them, and replayed them later.
That approach was fragile because it depended on constructor ordering
and required mprotect() to patch the read-only __mod_init_func section
at runtime.
This commit replaces the runtime hack with a post-link patching scheme:
1. Link with -Wl,-ld_classic,-no_fixup_chains to keep the classic
__mod_init_func pointer format (prevents ld64 from converting it
to __init_offsets).
2. Post-link, run patch_macho_initsection.py (python3 + lief) to
patch Mach-O section type flags from
MOD_INIT_FUNC_POINTERS/INIT_FUNC_OFFSETS to REGULAR, so dyld
skips them entirely.
3. Use the Mach-O auto-generated boundary symbols
section$start$__DATA_CONST$__mod_init_func /
section$end$__DATA_CONST$__mod_init_func, mapped via __asm()
labels in arch/sim/include/arch.h to the common _sinit[]/_einit[]
names used by lib_cxx_initialize().
Linux behavior is unchanged.
Changes:
- arch/sim/include/arch.h: add macOS __asm() declarations for
_sinit/_einit
- arch/sim/src/Makefile: drop sim_macho_init.c HEADSRC handling,
always pass -ld_classic,-no_fixup_chains on macOS, run
patch_macho_initsection.py after link when CONFIG_HAVE_CXXINITIALIZE
- arch/sim/src/sim/CMakeLists.txt: same for the CMake build
- arch/sim/src/patch_macho_initsection.py: new lief-based patcher
- arch/sim/src/sim/posix/sim_macho_init.c: deleted (135-line hack)
- libs/libc/misc/lib_cxx_initialize.c: remove
macho_call_saved_init_funcs special case; single unified loop
Testing:
- macOS (Ventura VM): verified lief patching with standalone test
(test_sinit7) confirming the constructor is deferred past main()
and only invoked when explicitly called via the _sinit/_einit loop.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
