BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
Fixed three bugs in the RP23XX PWM driver:
* setup_period: The previous divisor calculation used integer arithmetic
that caused overflow and loss of precision. The divider is now computed
as a 16-bit fixed-point value (div16) using 64-bit arithmetic, and
clamped to the valid hardware range (0x10 to 0xFFF).
* setup_pulse: The compare value was incorrectly scaled by TOP instead
of 65535, producing wrong duty cycles. The formula is now corrected
to ((duty * (top + 1)) / 65535) with an overflow guard.
* pwm_start: The driver was not updated as part of the breaking change
introduced in commit 4df80e19 ("!drivers/pwm: remove PWM_MULTICHAN
option"). Access to single channel API is now info->channels[0].duty
instead of info[0].duty.
Signed-off-by: Brunocor26 <bruno.correia@ubi.pt>
Add the autoleds driver for the three on-board user LEDs (LD5 red
PG10, LD6 green PG0, LD7 blue PG8; all active-low). Structure
mirrors boards/arm/stm32h5/nucleo-h563zi with the polarity and
initial-OFF state corrected for the active-low wiring.
* boards/Kconfig: ARCH_BOARD_NUCLEO_N657X0_Q selects ARCH_HAVE_LEDS
so the ARCH_LEDS prompt becomes available.
* arch/arm/src/stm32n6/stm32_idle.c: include <arch/board/board.h>
so LED_IDLE is defined and up_idle() actually calls into the
autoleds driver around WFI.
The existing nsh and ostest defconfigs do not pin CONFIG_ARCH_LEDS
and therefore inherit its Kconfig default (y when ARCH_HAVE_LEDS is
selected), so after this patch they include the autoleds driver by
default. This matches the convention on the comparable H5 and H7
Nucleo defconfigs, which also leave ARCH_LEDS at its default.
Tested on Nucleo-N657X0-Q: nsh and ostest still build, flash and
run. With CONFIG_ARCH_LEDS=y, green is steady at the NSH idle
prompt; red pulses on each IRQ but the on-time is too brief to be
clearly visible to the eye.
Signed-off-by: ImBonkers <samuelnlinden@pm.me>
The Ethernet MAC (57.11.4) was already configured in the code,
but it was necessary to configure the Transmit Descriptor (57.10.3)
in read format:
- Checksum Interface Control for IP, payload and pseudo-header
Add checks for Recceive Descriptor (57.10.4) in read format:
- Receive Descriptor 1 is valid from Receive Descriptor 3
- IP checksum was not bypassed
- IP header checksum error op IP payload checkerror is set
Testing with STM32 Nucleo-144 using iperf, improved transmission from
35 MBits/s to 50MBits/s.
Signed-off-by: Patrick José Pereira <patrickelectric@gmail.com>
Add support for the i.MX9 SAR ADC block.
Based on the arm64 version but slightly different init due to SCMI and
different channel mask for i.MX95.
The driver provides initialization, deinitialization, channel-mask
validation, and one-shot reads for the supported ADC channels. It also
handles the ADC clock bring-up, power-up sequence, calibration, and raw
12-bit result extraction from the per-channel data registers.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Update the destination register to r15 (PC) for test and clean
operations, as specified by the ARM926EJ-S Technical Reference
Manual (TRM). Using the wrong destination register prevented the
loop condition from updating correctly, resulting in an infinite
loop.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Now that time_t is unconditionally 64-bit (signed int64_t) and the
struct timespec fields tv_sec / tv_nsec are wide enough on their own,
the explicit (uint64_t)/(int64_t)/(int) casts that used to guard the
multiplications and subtractions in *_us / *_ms / *_ns helpers are no
longer needed. Drop them to keep the timekeeping math readable and
consistent with the previous sclock_t/time_t cleanup.
In the same spirit, this commit also:
* Normalises the printf-style format specifiers and casts used to
print tv_sec / tv_nsec / tv_usec values across arch/, drivers/,
fs/, sched/ and libs/. The prior code was a mix of
"%d"/"%u"/"%ld"/"%lu"/"%lld"/PRIu32/PRIu64 with matching
(int)/(unsigned long)/(long long)/PRIu* casts; some formats
truncated time_t on 32-bit hosts, others mismatched signedness or
width. Replace all such cases with the portable POSIX-recommended
forms:
- tv_sec (time_t, signed, impl-defined width) -> %jd + (intmax_t)
- tv_nsec (long, signed) -> %ld (no cast)
- tv_usec (suseconds_t / long) -> %ld (no cast)
Add #include <stdint.h> where required.
* Drops a few stale `(FAR const time_t *)&ts.tv_sec` casts and
related `(FAR struct tm *)` / `(const time_t *)` casts in
gmtime_r() / localtime_r() / gmtime() callers; ts.tv_sec is plain
time_t now and the casts only obscured the type.
* Fixes one overflow in fs/procfs/fs_procfscritmon.c where
all_time.tv_sec * 1000000 could overflow on 32-bit time_t before
being multiplied again; cast to uint64_t at the start.
No behavioural change.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
POSIX leaves the signedness of time_t and clock_t unspecified, but
mainstream implementations (Linux glibc/musl, the BSDs, macOS, RTEMS,
Zephyr's POSIX layer, Windows _time64) expose time_t as signed 64-bit.
NuttX has historically used uint64_t only because it was tied to the
CONFIG_SYSTEM_TIME64 knob; with that gone, switch:
time_t : uint64_t -> int64_t
clock_t : uint64_t -> int64_t
CLOCK_MAX: UINT64_MAX -> INT64_MAX
This lets (time_t)-1 sentinels, negative tick deltas, and host-side
headers behave as on every other POSIX system without source churn.
Headers updated:
- include/sys/types.h, include/limits.h, include/nuttx/clock.h
- include/nuttx/fs/hostfs.h (nuttx_time_t alias)
- include/nuttx/{mqueue.h,wdog.h,wqueue.h,timers/clkcnt.h}
Because clock_t is now signed 64-bit, the NuttX-internal sclock_t
alias becomes redundant: every sclock_t/SCLOCK_MAX use is folded
back to clock_t/CLOCK_MAX (notably in sched/wdog, sched/mqueue,
sched/sched, sched/clock, sched/timer, libs/libc/time, fs/vfs and
the drivers/arch consumers below).
Tick/period constants (NSEC_PER_SEC, USEC_PER_SEC, MSEC_PER_SEC,
SEC_PER_MIN, ...) in include/nuttx/clock.h are retyped from "long"
literals to INT64_C(...) so that 64-bit arithmetic no longer
depends on the host's long width.
Strip now-redundant (time_t)/(clock_t)/(unsigned long) casts and
unsigned-only branches across the tree:
- arch RTC / oneshot / tickless lowerhalfs:
arm: cxd56xx, efm32, imxrt, lc823450, max326xx, sam34, sama5,
samd5e5, samv7, stm32, stm32f7, stm32h7, stm32l4, stm32wb,
xmc4
mips: pic32mz sparc: bm3803 x86_64: intel64
risc-v/xtensa: espressif (esp_i2c[_slave], esp_rtc,
esp32c3{_i2c,_rtc,_wifi_adapter}, esp32{,s2,s3}_*),
mpfs_perf
- drivers: audio/tone, input/aw86225, power/pm/{activity,
stability}_governor, rpmsg/rpmsg_ping,
timers/{ds3231,mcp794xx,pcf85263,rx8010},
wireless/ieee80211/bcm43xxx, wireless/spirit/spirit_spi
- core: fs/vfs/{fs_poll,fs_timerfd}, mm/iob/iob_alloc,
libs/libc/{netdb/lib_dnscache,time/{lib_calendar2utc,
lib_time}}, net/icmp/icmp_pmtu, net/icmpv6/icmpv6_pmtu,
net/ipfrag, net/tcp/{tcp.h,tcp_timer},
net/utils/net_snoop, net/mld/mld_query (drop the now-dead
mld_mrc2mrd helper since signed math handles it directly),
sched/clock/{clock,clock_initialize},
sched/sched/{sched_profil,sched_setparam,sched_setscheduler},
sched/pthread/pthread_create,
sched/wdog/{wd_gettime,wd_start,wdog.h},
sched/timer/timer_gettime, sched/mqueue/*
Flip the few in-tree printf format strings that assumed an
unsigned 64-bit tv_sec:
* drivers/rpmsg/rpmsg_ping.c PRIu64 -> PRId64
* arch/xtensa/src/esp32{,s2,s3}/esp32*_oneshot_lowerhalf.c
PRIu32 (already wrong) -> PRId64
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The 32-bit system clock has a limited range (~497 days) and the
configuration knob is no longer worth the complexity given that
practically every modern target already enables it. Make 64-bit
time_t/clock_t/sclock_t/nuttx_time_t the only supported flavor.
Specifically:
- Drop the SYSTEM_TIME64 Kconfig option and its dependent
PERF_OVERFLOW_CORRECTION/HRTIMER guards in sched/Kconfig.
- Remove every #ifdef CONFIG_SYSTEM_TIME64 branch in headers
(include/{sys/types.h,limits.h,inttypes.h,nuttx/clock.h,
nuttx/fs/hostfs.h}) and core code paths
(sched/clock/clock.h, drivers/power/pm/pm_procfs.c,
drivers/rpmsg/rpmsg_ping.c, fs/procfs/fs_procfsuptime.c,
libs/libc/wqueue/work_usrthread.c,
arch/avr/src/avrdx/avrdx_timerisr_tickless_alarm.c).
- Strip CONFIG_SYSTEM_TIME64=y from every board defconfig.
- Update Documentation/guides/rust.rst accordingly.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Introduce minimal chip support for the STMicro STM32N6 family
(Cortex-M55, ARMv8.1-M with TrustZone and FPU), sufficient to bring
up an NSH console over USART1.
Scope (deliberately minimal first drop):
- Chip selector ARCH_CHIP_STM32N6 wired into arch/arm/Kconfig and
chip-name mapping ("stm32n6").
- Sub-Kconfig under arch/arm/src/stm32n6 with the STM32N657X0 chip
selector and a single user-selectable USART (USART1).
- Boot path: stm32_start with a naked dispatcher that clears the
boot-ROM MSPLIM/PSPLIM stack limits before any compiler-emitted
prologue, then runs vector relocation and SRAM-only heap init.
The chip runs entirely in the Secure state; SAU is left in its
reset configuration.
- PLL1-based clock tree fed from HSI64 targeting 200 MHz CPU, with
USART1 kernel-clock routed to HSI for a predictable BRR that is
independent of any later clock change.
- Low-level USART driver with full serial framework support.
stm32_serial.c is adapted from arch/arm/src/stm32h5/stm32_serial.c
(sibling ARMv8-M Mainline port with the same USART IP), stripped
of DMA-RX, LPUART, the per-USART2..5 plumbing, RS-485 driver-enable,
TIOCSINVERT/SWAP and HALFDUPLEX paths.
- SysTick system timer.
- GPIO, PWR and RCC helpers.
TrustZone, MPU, I/D-cache and Helium (MVE) are left disabled to
minimise bring-up surface; these will be added in follow-up patches
alongside the drivers that need them.
Signed-off-by: ImBonkers <samuelnlinden@pm.me>
BREAKING CHANGE: remove PWM_MULTICHAN option
PWM_MULTICHAN option is redundant, we can just set CONFIG_PWM_NCHANNELS > 1.
At default CONFIG_PWM_NCHANNELS is set to 1, so the default behavior is preserved.
Access to single channel API is now `info->channels[0].XXX` instead of `info->XXX`
This is the first step to simplify PWM implementation and make it more portable.
Signed-off-by: raiden00pl <raiden00@railab.me>
The goal is to only execute recipes when there is an actual change in
the prerequisites.
There are several issues which cause the nuttx binary target to be
re-made every time the top level make is run.
1. Previously the target nuttx$(EXEEXT), was used, but make resolved
this in the relative directory make -C $(ARCH_SRC), and couldn’t find
it (need an absolute path: `$(TOPDIR)/..).
2. The .tmp prerequisite for nuttx was always deleted
3. libboard's recipe had a sub-make which may or may not update that
target. This was a phony target, and was therefore always considered out
of date.
These issues were causing the nuttx recipe to be run every make, which
was hiding some missing prerequisites:
1. the .config is a prerequisite for the .tmp target
2. libapps.a (and other linklibs) are pre-requisites for nuttx
Changes:
The changes are only in the build system, and only for arm.
Track nuttx$(EXEEXT) via vpath so Make knows when it's already up to
date without an explicit path. Add $(TOPDIR)/.config as a dependency
to the linker script preprocessing so config changes trigger
re-preprocessing.
Keep the .tmp linker script on disk (clean already removes it) so
timestamp-based dependency checking works across builds. These .tmp
files need to be added to the gitignore or the CI will complain.
Use FORCE pattern for board/libboard to ensure it's always checked
but use the actual library file as the link dependency so nuttx is
only re-linked when library content changes. Add staging libs as
dependency to nuttx link rule so changed app libs trigger re-link.
Signed-off-by: Liam Hickey <williamhickey@geotab.com>
The STM32 DMA NDTR/CNDTR transfer-count register is 16 bits wide on
every STM32 series the in-tree driver supports (IPv1 CNDTR, IPv2
SxNDTR). spi_exchange()'s DMA path forwarded the caller's full
nwords to stm32_dmasetup(), so a single SPI_EXCHANGE() of >= 65536
words silently programmed NDTR to (nwords & 0xffff). When the
truncated count was zero - the typical case for an exact 64 KiB
transfer (flash erase block, FAT cluster, common DMA staging
buffer) - the stream completed instantly with no transfer-complete
interrupt and the caller deadlocked in spi_dmarxwait().
Walk the request in chunks of at most 65535 words inside the
existing DMA branch, reusing the same spi_dma{rx,tx}{setup,start,
wait}() sequence per chunk. Single-descriptor transfers (every
in-tree caller today) are byte-for-byte identical. CONFIG_SPI_TRIGGER
is honored for the first chunk only; subsequent chunks must run
unconditionally because re-arming between chunks of one logical
exchange was never part of the SPI_TRIGGER contract.
Drive-by: rescale priv->buflen-clamped nwords so the DMA
descriptor matches the actually-copied byte count, promote the
spiinfo() format specifier from %d to %zu, and fix two adjacent
comment typos.
See the PR description for reproduction, NSH log and benchmark
numbers (5.12 MB/s, 97.5% of SCK/8 @ 42 MHz on STM32F407 + W25Q128).
Signed-off-by: Jinji Cui <113000688+cjj66619@users.noreply.github.com>
PendSV is the deferred half of the Cortex-M context-switch path: a
higher-priority ISR that wakes a task sets PendSV pending and returns,
and PendSV then performs the register save/restore. This pattern is
only safe when PendSV runs at the lowest priority - otherwise a
peripheral ISR can preempt the context switch mid-update and corrupt
thread state.
The previous write of DEFPRIORITY32 to NVIC_SYSH12_15_PRIORITY in
up_irqinitialize() leaves PendSV at NVIC_SYSH_PRIORITY_DEFAULT (0x80),
the same priority as peripheral IRQs. Read-modify-write the SHPR3 to
lower only the PendSV byte to NVIC_SYSH_PRIORITY_MIN.
This is the canonical ARM Cortex-M priority arrangement and it matches
e.g. this reference:
https://nuttx.apache.org/docs/latest/guides/zerolatencyinterrupts.html (although
worked with a three-bit priority system)
This patch hardens up_irqinitialize against future peripheral-IRQ
prioritisation.
Signed-off-by: Daniel Fanache <dan@rts.ro>
At system startup, the NVIC was configured for proper default priority
only for the first three IPR registers, even though the loop was
executed 13 times - due to a gotcha on what the `NVIC_IRQ_PRIORITY(i)`
macro returns.
IRQs 12-51 stayed at the reset priority of 0 - highest in the system;
so any peripherals issuing those interrupts will shoot through
critical sections that rely on
BASEPRI = NVIC_SYSH_PRIORITY_DEFAULT (0x80).
This can corrupt the TCB ready-to-run list and semaphore wait queues;
this is hard to reproduce (e.g. in ostest) because it requires a
peripheral ISR to land inside a critical section, but the failure
modes range from hangs to wild pointer crashes once it does.
In my case I had SPI and I2C peripherals that were issuing IRQs and
were preempting scheduler and semaphore list operations, causing
corruption.
Step the loop by four and bound it with RP23XX_IRQ_NEXTINT so every
IPR covering IRQs 0..51 is written once with DEFPRIORITY32.
Signed-off-by: Daniel Fanache <dan@rts.ro>
The host interrupt callback was incorrectly using the wrong IRQ for
disconnected. In host mode the same IRQ is used for connect/disconnected
and it must check a status bit to know which one.
When a USB device was unplugged, the host channels were free'd,
but if they happen to be mid-transfer, that transfer was never cancelled
so the USB hardware might still be trying to perfrom a transfer after
was free'd. Fixed by cancelling any transfers on free.
Signed-off-by: daniellizewski <daniellizewski@geotab.com>
Use GPIO_MODE_INPUT for STM32F1 pinmap entries that are configured as
GPIO_INPUT instead of carrying GPIO_MODE_2MHz.
For STM32F1 the MODE field selects output speed only for output or
alternate-function output pins. stm32_configgpio() forces input pins to
input mode regardless of the encoded MODE bits.
From arch/arm/src/stm32/stm32_gpio.c:
311 /* Decode the mode and configuration */
312
313 regval = getreg32(cr);
314
315 if (input)
316 {
317 /* Input.. force mode = INPUT */
318
319 modecnf = 0;
320 }
321 else
322 {
323 /* Output or alternate function */
324
325 modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT;
326 }
Signed-off-by: raiden00pl <raiden00@railab.me>
NuttX uses Quadrature Encoder lower half driver to internal QE from
MCUs and also with Magnetic Rotary Encoder sensors. But when the
STM32 QE is not enabled, the board code will try to compile the
stm32_qencoder.c because Magnetic Rotary Encoders enables the
CONFIG_SENSORS_QENCODER. This patch fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
BREAKING: In an effort to simplify NuttX initialization, NSH_ARCHINIT is
removed. board_app_initialize is also removed. BOARD_LATE_INITIALIZE now
performs all board initialization logic, and is by default enabled. All
references to these symbols are removed. BOARDIOC_INIT remains, but will
result in -ENOTTY when called. It is to be removed in a later commit.
Quick fix: Boards relying on NSH_ARCHINIT should now enable
CONFIG_BOARD_LATE_INITIALIZE instead. If the application needs
fine-grained control over board initialization from userspace, the logic
performed by BOARDIOC_INIT may be copied to the board_finalinitialize
function and used instead via BOARDIOC_FINALINIT. All
board_app_initialize logic provided by NuttX is now moved to
board_late_initialize, and the same should be done for out-of-tree
boards.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
The register index layout for D16-D31 and FPU_CONTEXT_REGS was guarded
by CONFIG_ARM_HAVE_DPFPU32 (hardware capability) in three header files,
but all save/restore code in the corresponding .S files gates on
CONFIG_ARM_DPFPU32 (software enable).
These two macros are distinct:
CONFIG_ARM_HAVE_DPFPU32 - set by chip via 'select'; means hardware
has D16-D31 registers
CONFIG_ARM_DPFPU32 - user-selectable; means software has chosen
to use D16-D31 (requires hardware support)
When ARM_HAVE_DPFPU32=y and ARM_DPFPU32=n, the header defined
REG_FPSCR at offset 64 and FPU_CONTEXT_REGS=65, while the assembly
only saved S0-S31+FPSCR (33 words), placing FPSCR at offset 32.
This mismatch causes incorrect register access and wrong xcptcontext
sizing.
Signed-off-by: yaojiaqi <yaojiaqi@lixiang.com>
DLASTSGA needs to be offest for TCM backdoor address.
Cleanup as well using inline helper for calculuation.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Always allocate per-file can_reader on open so write-only descriptors get msgalign / ioctl state; free that context on close when it was never linked into cd_readers (fixes leak).
Cap each drain loop (20×500 ms) so close() cannot block forever when bxCAN retries without ACK or dev_txempty never clears.
Fix stm32can_vputreg debug log to print the written value (correct parameter name).
Signed-off-by: Alexey Matveev <tippet@yandex.ru>
In sporadic cases it is possible that a SPI exchange returns stale RX data from the DCACHE.
This occurs when:
- DCACHE is enabled
- DMA is used
The impact of this can be hard to debug and vanishes when the timing even changes minimally.
This is caused by the DCACHE being invalidated before the actual DMA transaction starts which violates
the recommendations from AN4839 and also does not match the implementation of other drivers on the STM32H7/STM32F7.
Fixed by invalidating the DCACHE right before the actual read, which matches the implementation
of the STM32F7 SPI driver.
Signed-off-by: alexcekay <alexander@auterion.com>
Enable USART3 support for STM32F412 and use it as the default NUCLEO-F412ZG nsh console path.
The ST-LINK virtual COM port on this board is wired to USART3 on PD8/PD9. Restore USART2 to its header-pin routing, switch the nsh defconfig to USART3, and update the board documentation to match the shipped solder-bridge configuration described in issue #17722.
Signed-off-by: aviralgarg05 <gargaviral99@gmail.com>
Fixed a few bugs in the initial stm32_usbdrdhost.c implementation
when using a USB hub. Fixed fault when freeing control endpoints.
Fixed crash when disconnecting devices from hubs due ot use after free.
Signed-off-by: daniellizewski <daniellizewski@geotab.com>
fix compilation error for CONFIG_SERIAL_TERMIOS=y
chip/stm32_serial_v2.c:923:35: error: 'struct up_dev_s' has no member named 'rxftcfg'
923 | regval |= USART_CR3_RXFTCFG(priv->rxftcfg);
Signed-off-by: raiden00pl <raiden00@railab.me>
Added stm32_usbdrdhost.c which adds USB FS host mode support using the
embedded PHY. Added Kconfig to select Device or Host.
Example config nucleo-h563zi:usbmsc added to test functionality
Signed-off-by: daniellizewski <daniellizewski@geotab.com>
When the macro SDADC_HAVE_TIMER is enabled, a compilation
error will occur due to the missing semicolon after the variable.
Signed-off-by: zhanxiaoqi <zhanxiaoqi@bytedance.com>
