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!drivers/pwm: remove PWM_MULTICHAN option

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BREAKING CHANGE: remove PWM_MULTICHAN option

PWM_MULTICHAN option is redundant, we can just set CONFIG_PWM_NCHANNELS > 1.
At default CONFIG_PWM_NCHANNELS is set to 1, so the default behavior is preserved.
Access to single channel API is now `info->channels[0].XXX` instead of `info->XXX`

This is the first step to simplify PWM implementation and make it more portable.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2025-01-10 10:41:22 +01:00 • committed by Matteo Golin
parent 7a04cddb78
commit 4df80e1928
105 changed files with 333 additions and 951 deletions
Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/Kconfig
View file

@ -319,7 +319,6 @@ config ARCH_CHIP_NRF52
#select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_FPU
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_DMA_NO_FLASH_TRANSFER
---help---
@ -328,7 +327,6 @@ config ARCH_CHIP_NRF52
config ARCH_CHIP_NRF53
bool "Nordic nRF53"
select ARCH_CORTEXM33
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_DMA_NO_FLASH_TRANSFER
depends on EXPERIMENTAL
---help---
@ -337,7 +335,6 @@ config ARCH_CHIP_NRF53
config ARCH_CHIP_NRF91
bool "Nordic nRF91"
select ARCH_CORTEXM33
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_TRUSTZONE
select ARCH_HAVE_TICKLESS
select ARCH_DMA_NO_FLASH_TRANSFER
@ -373,7 +370,6 @@ config ARCH_CHIP_RP2040
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET
select ARM_HAVE_WFE_SEV
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_BOARD_COMMON
select ARCH_HAVE_CUSTOM_TESTSET
---help---
@ -389,7 +385,6 @@ config ARCH_CHIP_RP23XX
select ARM_HAVE_DSP
select ARCH_HAVE_FPU
select ARCH_HAVE_CUSTOM_TESTSET
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_BOARD_COMMON
---help---
Raspberry Pi RP23XX architectures (ARM dual Cortex-M33 or RISC-V).

1
arch/arm/src/at32/Kconfig
View file

@ -3651,7 +3651,6 @@ config AT32_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on AT32_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

56
arch/arm/src/at32/at32_pwm.c
View file

@ -2168,11 +2168,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel,
pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n",
priv->timid, channel, duty);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(channel == priv->channels[0].channel);
DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
#endif
/* Get the reload values */
reload = pwm_arr_get(dev);
@ -3219,13 +3214,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
pwminfo("TIM%u channel: %u frequency: %" PRIx32 " duty: %08" PRIx32
" count: %" PRIx32 "\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
DEBUGASSERT(info->frequency > 0);
/* Channel specific setup */
duty = info->duty;
duty = info->channels[0].duty;
channel = priv->channels[0].channel;
/* Disable all interrupts and DMA requests, clear all pending status */
@ -3254,7 +3249,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* assured us that the count value is within range).
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Save the remaining count and the number of counts that will have
* elapsed on the first interrupt.
@ -3265,7 +3260,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* value.
*/
priv->prev = pwm_pulsecount(info->count);
priv->prev = pwm_pulsecount(info->channels[0].count);
pwm_rcr_update(dev, priv->prev - 1);
/* Generate an update event to reload the prescaler. This should
@ -3278,8 +3273,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* update event.
*/
priv->count = info->count;
priv->curr = pwm_pulsecount(info->count - priv->prev);
priv->count = info->channels[0].count;
priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev);
pwm_rcr_update(dev, priv->curr - 1);
}
@ -3308,12 +3303,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
goto errout;
}
/* Setup update interrupt. If info->count is > 0, then we can be
* assured that pwm_pulsecount_start() has already verified: (1) that this
* is an advanced timer, and that (2) the repetition count is within range.
/* Setup update interrupt. If info->channels[0].count is > 0, then we can
* be assured that pwm_pulsecount_start() has already verified: (1) that
* this is an advanced timer, and that (2) the repetition count is within
* range.
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Clear all pending interrupts and enable the update interrupt. */
@ -3467,16 +3463,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
uint8_t channel = 0;
ub16_t duty = 0;
int ret = OK;
#ifdef CONFIG_PWM_MULTICHAN
int i = 0;
int j = 0;
#endif
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
#endif
{
#ifdef CONFIG_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -3509,10 +3500,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
ret = -EINVAL;
goto errout;
}
#else
duty = info->duty;
channel = priv->channels[0].channel;
#endif
/* Update duty cycle */
@ -3521,9 +3508,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
{
goto errout;
}
#ifdef CONFIG_PWM_MULTICHAN
}
#endif
}
errout:
@ -3554,19 +3539,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_PWM_MULTICHAN)
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#else
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n",
priv->timid, priv->channels[0].channel,
info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* TODO: what if we have pwm running and we want disable some channels ? */
@ -4172,14 +4148,14 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev,
/* Generate an indefinite number of pulses */
if (info->count == 0)
if (info->channels[0].count == 0)
{
return pwm_start(dev, info);
}
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting)
* REVISIT: verify if TIMTYPE_COUNTUP16_N works with it
@ -4188,7 +4164,7 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev,
if (priv->timtype != TIMTYPE_ADVANCED)
{
pwmerr("ERROR: TIM%u cannot support pulse count: %" PRIx32 "\n",
priv->timid, info->count);
priv->timid, info->channels[0].count);
return -EPERM;
}
}
@ -4213,7 +4189,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (info->frequency == priv->frequency)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
@ -4233,9 +4208,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
}
#else
ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
}
else
{

2
arch/arm/src/at32/at32_pwm.h
View file

@ -358,7 +358,7 @@
PWM_TIM20_CHANNEL3 + PWM_TIM20_CHANNEL4 + \
PWM_TIM20_CHANNEL5 + PWM_TIM20_CHANNEL6)
#else /* !CONFIG_PWM_MULTICHAN */
#else /* !CONFIG_AT32_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:

7
arch/arm/src/cxd56xx/cxd56_pwm.c
View file

@ -394,13 +394,13 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
uint32_t phase;
int ret;
if (info->duty <= 0)
if (info->channels[0].duty <= 0)
{
/* Output low level if duty cycle is almost 0% */
PWM_REG(priv->ch)->EN = 0x0;
}
else if (info->duty >= 65536)
else if (info->channels[0].duty >= 65536)
{
/* Output high level if duty cycle is almost 100% */
@ -409,7 +409,8 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
}
else
{
ret = convert_freq2period(info->frequency, info->duty, &param, &phase);
ret = convert_freq2period(info->frequency, info->channels[0].duty,
&param, &phase);
if (ret < 0)
{
return -EINVAL;

12
arch/arm/src/efm32/efm32_pwm.c
View file

@ -360,13 +360,14 @@ static int pwm_timer(struct efm32_pwmtimer_s *priv,
#ifdef CONFIG_PWM_PULSECOUNT
pwminfo("TIMER%d channel: %d frequency: %d duty: %08x count: %d\n",
priv->timid, priv->channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
#else
pwminfo("TIMER%d channel: %d frequency: %d duty: %08x\n",
priv->timid, priv->channel, info->frequency, info->duty);
priv->timid, priv->channel, info->frequency,
info->channels[0].duty);
#endif
DEBUGASSERT(info->frequency > 0 && info->duty >= 0 &&
info->duty < uitoub16(100));
DEBUGASSERT(info->frequency > 0 && info->channels[0].duty >= 0 &&
info->channels[0].duty < uitoub16(100));
efm32_timer_reset(priv->base);
@ -403,7 +404,8 @@ static int pwm_timer(struct efm32_pwmtimer_s *priv,
pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval);
regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16;
regval = (info->channels[0].duty *
pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16;
pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET, regval);
/* pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval); */

20
arch/arm/src/ht32f491x3/Kconfig
View file

@ -63,7 +63,7 @@ config HT32F491X3_TMR1
config HT32F491X3_TMR1_PWM
bool "TMR1 PWM output"
default n
depends on HT32F491X3_TMR1 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR1 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR1.
@ -85,7 +85,7 @@ config HT32F491X3_TMR2
config HT32F491X3_TMR2_PWM
bool "TMR2 PWM output"
default n
depends on HT32F491X3_TMR2 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR2 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR2.
@ -107,7 +107,7 @@ config HT32F491X3_TMR3
config HT32F491X3_TMR3_PWM
bool "TMR3 PWM output"
default n
depends on HT32F491X3_TMR3 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR3 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR3.
@ -129,7 +129,7 @@ config HT32F491X3_TMR4
config HT32F491X3_TMR4_PWM
bool "TMR4 PWM output"
default n
depends on HT32F491X3_TMR4 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR4 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR4.
@ -165,7 +165,7 @@ config HT32F491X3_TMR9
config HT32F491X3_TMR9_PWM
bool "TMR9 PWM output"
default n
depends on HT32F491X3_TMR9 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR9 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR9.
@ -187,7 +187,7 @@ config HT32F491X3_TMR10
config HT32F491X3_TMR10_PWM
bool "TMR10 PWM output"
default n
depends on HT32F491X3_TMR10 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR10 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR10.
@ -208,7 +208,7 @@ config HT32F491X3_TMR11
config HT32F491X3_TMR11_PWM
bool "TMR11 PWM output"
default n
depends on HT32F491X3_TMR11 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR11 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR11.
@ -229,7 +229,7 @@ config HT32F491X3_TMR12
config HT32F491X3_TMR12_PWM
bool "TMR12 PWM output"
default n
depends on HT32F491X3_TMR12 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR12 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR12.
@ -251,7 +251,7 @@ config HT32F491X3_TMR13
config HT32F491X3_TMR13_PWM
bool "TMR13 PWM output"
default n
depends on HT32F491X3_TMR13 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR13 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR13.
@ -272,7 +272,7 @@ config HT32F491X3_TMR14
config HT32F491X3_TMR14_PWM
bool "TMR14 PWM output"
default n
depends on HT32F491X3_TMR14 && PWM && !PWM_MULTICHAN
depends on HT32F491X3_TMR14 && PWM && PWM_NCHANNELS = 1
---help---
Enable lower-half PWM support on TMR14.

15
arch/arm/src/ht32f491x3/ht32f491x3_pwm.c
View file

@ -73,13 +73,13 @@ struct ht32f491x3_pwmcfg_s
struct ht32f491x3_pwmtimer_s
{
const struct pwm_ops_s *ops;
const struct pwm_ops_s *ops;
FAR const struct ht32f491x3_pwmcfg_s *cfg;
uint32_t gpio_clken;
uintptr_t gpio_base;
uint8_t channel;
uint8_t pin;
uint8_t af;
uint32_t gpio_clken;
uintptr_t gpio_base;
uint8_t channel;
uint8_t pin;
uint8_t af;
};
/****************************************************************************
@ -345,7 +345,8 @@ static int pwm_timer(FAR struct ht32f491x3_pwmtimer_s *priv,
}
reload -= 1u;
pulse = (uint32_t)(((uint64_t)reload * info->duty + 0x8000ull) >> 16);
pulse = (uint32_t)(((uint64_t)reload *
info->channels[0].duty + 0x8000ull) >> 16);
if (pulse > reload)
{
pulse = reload;

1
arch/arm/src/imxrt/Kconfig
View file

@ -298,7 +298,6 @@ config IMXRT_FLEXCAN2_FD
config IMXRT_FLEXPWM
bool
default n
select ARCH_HAVE_PWM_MULTICHAN
config IMXRT_LPI2C
bool

29
arch/arm/src/imxrt/imxrt_flexpwm.c
View file

@ -808,11 +808,7 @@ static int pwm_change_freq(struct pwm_lowerhalf_s *dev,
uint8_t channel)
{
struct imxrt_flexpwm_s *priv = (struct imxrt_flexpwm_s *)dev;
#ifdef CONFIG_PWM_MULTICHAN
uint8_t shift = (info->channels[channel].channel - 1) >> 1;
#else
uint8_t shift = priv->modules[0].module - 1;
#endif
uint16_t regval;
uint16_t olddiv = getreg16(priv->base + IMXRT_FLEXPWM_SM0VAL1_OFFSET
+ MODULE_OFFSET * shift);
@ -1219,7 +1215,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
{
for (int i = 0; i < PWM_NCHANNELS; i++)
{
#ifdef CONFIG_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -1233,9 +1228,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
{
ret = pwm_change_freq(dev, info, i);
}
#else
ret = pwm_change_freq(dev, info, i);
#endif
}
/* Save current frequency */
@ -1246,7 +1238,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
}
}
#ifdef CONFIG_PWM_MULTICHAN
for (int i = 0; ret == OK && i < PWM_NCHANNELS; i++)
{
/* Break the loop if all following channels are not configured */
@ -1268,15 +1259,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
ldok_map |= 1 << ((info->channels[i].channel - 1) >> 1);
}
}
#else
/* Enable PWM output just for first channel */
ret = pwm_set_output(dev, priv->modules[0].module, info->duty);
/* Remember the channel number in bitmap */
ldok_map = 1 << (priv->modules[0].module - 1);
#endif /* CONFIG_PWM_MULTICHAN */
/* Set Load Okay bits */
@ -1312,7 +1294,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev)
uint8_t shift;
uint16_t regval;
#ifdef CONFIG_PWM_MULTICHAN
for (int i = 0; i < priv->modules_num; i++)
{
/* Skip settings if channel is not configured */
@ -1330,16 +1311,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev)
regval = OUTEN_PWMB_EN(0 << shift);
putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET);
}
#else
shift = priv->modules[0].module - 1;
regval = OUTEN_PWMA_EN(0 << shift);
putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET);
regval = OUTEN_PWMB_EN(0 << shift);
putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET);
#endif /* CONFIG_PWM_MULTICHAN */
return OK;
}

9
arch/arm/src/kinetis/kinetis_pwm.c
View file

@ -365,10 +365,11 @@ static int pwm_timer(struct kinetis_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
pwminfo("FTM%d channel: %d frequency: %" PRId32 " duty: %08" PRIx32 "\n",
priv->tpmid, priv->channel, info->frequency, info->duty);
priv->tpmid, priv->channel, info->frequency,
info->channels[0].duty);
DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
info->duty < uitoub16(100));
DEBUGASSERT(info->frequency > 0 && info->channels[0].duty > 0 &&
info->channels[0].duty < uitoub16(100));
/* Calculate optimal values for the timer prescaler and for the timer
* modulo register. If' frequency' is the desired frequency, then
@ -432,7 +433,7 @@ static int pwm_timer(struct kinetis_pwmtimer_s *priv,
* duty cycle = cv / modulo (fractional value)
*/
cv = b16toi(info->duty * modulo + b16HALF);
cv = b16toi(info->channels[0].duty * modulo + b16HALF);
pwminfo("FTM%d PCLK: %" PRId32 " frequency: %" PRIx32 " FTMCLK: %" PRIx32
" prescaler: %d modulo: %" PRId32 " c0v: %" PRId32 "\n",

9
arch/arm/src/kl/kl_pwm.c
View file

@ -331,10 +331,11 @@ static int pwm_timer(struct kl_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
pwminfo("TPM%d channel: %d frequency: %" PRId32 " duty: %08" PRIx32 "\n",
priv->tpmid, priv->channel, info->frequency, info->duty);
priv->tpmid, priv->channel, info->frequency,
info->channels[0].duty);
DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
info->duty < uitoub16(100));
DEBUGASSERT(info->frequency > 0 && info->channels[0].duty > 0 &&
info->channels[0].duty < uitoub16(100));
/* Calculate optimal values for the timer prescaler and for the timer
* modulo register. If' frequency' is the desired frequency, then
@ -398,7 +399,7 @@ static int pwm_timer(struct kl_pwmtimer_s *priv,
* duty cycle = cv / modulo (fractional value)
*/
cv = b16toi(info->duty * modulo + b16HALF);
cv = b16toi(info->channels[0].duty * modulo + b16HALF);
pwminfo("TPM%d PCLK: %" PRId32 " frequency: %" PRId32 " TPMCLK: %" PRId32
" prescaler: %d modulo: %" PRId32 " c0v: %" PRId32 "\n",

1
arch/arm/src/lpc17xx_40xx/Kconfig
View file

@ -348,7 +348,6 @@ config LPC17_40_PWM0
config LPC17_40_PWM1
bool "PWM1"
select ARCH_HAVE_PWM_MULTICHAN
default n
config LPC17_40_PWM1_PIN

9
arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c
View file

@ -268,8 +268,13 @@ static int mcpwm_timer(struct lpc17_40_mcpwmtimer_s *priv,
flags = enter_critical_section();
putreg32(info->frequency, LPC17_40_MCPWM_LIM0); /* Set PWMMR0 = number of counts */
putreg32(info->duty, LPC17_40_MCPWM_MAT0); /* Set PWM cycle */
/* Set PWMMR0 = number of counts */
putreg32(info->frequency, LPC17_40_MCPWM_LIM0);
/* Set PWM cycle */
putreg32(info->channels[0].duty, LPC17_40_MCPWM_MAT0);
leave_critical_section(flags);
mcpwm_dumpregs(priv, "After starting");

6
arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c
View file

@ -296,7 +296,6 @@ static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv,
pwm_getreg(priv, LPC17_40_PWM_PC_OFFSET));
pwminfo(" MCR: %04x\n",
pwm_getreg(priv, LPC17_40_PWM_MCR_OFFSET));
#ifdef CONFIG_PWM_MULTICHAN
pwminfo(" 0: %08x 1: %08x 2: %08x 3: %08x\n",
pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
@ -306,7 +305,6 @@ static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv,
pwm_getreg(priv, LPC17_40_PWM_MR4_OFFSET),
pwm_getreg(priv, LPC17_40_PWM_MR5_OFFSET),
pwm_getreg(priv, LPC17_40_PWM_MR6_OFFSET));
#endif
}
#endif
@ -341,9 +339,6 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv,
putreg32(mr0_freq, LPC17_40_PWM1_MR0); /* Set PWMMR0 = number of counts */
#ifndef CONFIG_PWM_MULTICHAN
putreg32(info->duty, LPC17_40_PWM1_MR1); /* Set PWM cycle */
#else
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
{
switch (priv->channels[i].channel)
@ -398,7 +393,6 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv,
}
}
}
#endif
#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
pcrval |= PWMENA1;

54
arch/arm/src/nrf52/nrf52_pwm.c
View file

@ -68,9 +68,6 @@ struct nrf52_pwm_s
uint32_t ch1_pin; /* Channel 2 pin */
uint32_t ch2_pin; /* Channel 3 pin */
uint32_t ch3_pin; /* Channel 4 pin */
#ifndef CONFIG_PWM_MULTICHAN
uint8_t channel; /* Assigned channel */
#endif
/* Sequence 0 */
@ -148,9 +145,6 @@ struct nrf52_pwm_s g_nrf52_pwm0 =
#ifdef CONFIG_NRF52_PWM0_CH3
.ch3_pin = NRF52_PWM0_CH3_PIN,
#endif
#ifndef CONFIG_PWM_MULTICHAN
.channel = CONFIG_NRF52_PWM0_CHANNEL
#endif
};
#endif
@ -173,9 +167,6 @@ struct nrf52_pwm_s g_nrf52_pwm1 =
#ifdef CONFIG_NRF52_PWM1_CH3
.ch3_pin = NRF52_PWM1_CH3_PIN,
#endif
#ifndef CONFIG_PWM_MULTICHAN
.channel = CONFIG_NRF52_PWM1_CHANNEL
#endif
};
#endif
@ -198,9 +189,6 @@ struct nrf52_pwm_s g_nrf52_pwm2 =
#ifdef CONFIG_NRF52_PWM2_CH3
.ch3_pin = NRF52_PWM2_CH3_PIN,
#endif
#ifndef CONFIG_PWM_MULTICHAN
.channel = CONFIG_NRF52_PWM2_CHANNEL
#endif
};
#endif
@ -223,9 +211,6 @@ struct nrf52_pwm_s g_nrf52_pwm3 =
#ifdef CONFIG_NRF52_PWM3_CH3
.ch3_pin = NRF52_PWM3_CH3_PIN,
#endif
#ifndef CONFIG_PWM_MULTICHAN
.channel = CONFIG_NRF52_PWM3_CHANNEL
#endif
};
#endif
@ -568,9 +553,7 @@ static int nrf52_pwm_start(struct pwm_lowerhalf_s *dev,
{
struct nrf52_pwm_s *priv = (struct nrf52_pwm_s *)dev;
int ret = OK;
#ifdef CONFIG_PWM_MULTICHAN
int i = 0;
#endif
int i;
DEBUGASSERT(dev);
@ -588,29 +571,24 @@ static int nrf52_pwm_start(struct pwm_lowerhalf_s *dev,
}
}
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
{
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
{
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
{
break;
}
/* Set output if channel configured */
if (info->channels[i].channel != 0)
{
ret = nrf52_pwm_duty(priv,
(info->channels[i].channel - 1),
info->channels[i].duty);
}
break;
}
#else
ret = nrf52_pwm_duty(priv, priv->channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
/* Set output if channel configured */
if (info->channels[i].channel != 0)
{
ret = nrf52_pwm_duty(priv,
(info->channels[i].channel - 1),
info->channels[i].duty);
}
}
/* Start sequence 0 */

49
arch/arm/src/nrf53/nrf53_pwm.c
View file

@ -68,9 +68,6 @@ struct nrf53_pwm_s
uint32_t ch1_pin; /* Channel 2 pin */
uint32_t ch2_pin; /* Channel 3 pin */
uint32_t ch3_pin; /* Channel 4 pin */
#ifndef CONFIG_PWM_MULTICHAN
uint8_t channel; /* Assigned channel */
#endif
/* Sequence 0 */
@ -148,9 +145,6 @@ struct nrf53_pwm_s g_nrf53_pwm0 =
#ifdef CONFIG_NRF53_PWM0_CH3
.ch3_pin = NRF53_PWM0_CH3_PIN,
#endif
#ifndef CONFIG_PWM_MULTICHAN
.channel = CONFIG_NRF53_PWM0_CHANNEL
#endif
};
#endif
@ -173,9 +167,6 @@ struct nrf53_pwm_s g_nrf53_pwm1 =
#ifdef CONFIG_NRF53_PWM1_CH3
.ch3_pin = NRF53_PWM1_CH3_PIN,
#endif
#ifndef CONFIG_PWM_MULTICHAN
.channel = CONFIG_NRF53_PWM1_CHANNEL
#endif
};
#endif
@ -198,9 +189,6 @@ struct nrf53_pwm_s g_nrf53_pwm2 =
#ifdef CONFIG_NRF53_PWM2_CH3
.ch3_pin = NRF53_PWM2_CH3_PIN,
#endif
#ifndef CONFIG_PWM_MULTICHAN
.channel = CONFIG_NRF53_PWM2_CHANNEL
#endif
};
#endif
@ -543,9 +531,7 @@ static int nrf53_pwm_start(struct pwm_lowerhalf_s *dev,
{
struct nrf53_pwm_s *priv = (struct nrf53_pwm_s *)dev;
int ret = OK;
#ifdef CONFIG_PWM_MULTICHAN
int i = 0;
#endif
DEBUGASSERT(dev);
@ -563,29 +549,24 @@ static int nrf53_pwm_start(struct pwm_lowerhalf_s *dev,
}
}
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
{
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
{
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
{
break;
}
/* Set output if channel configured */
if (info->channels[i].channel != 0)
{
ret = nrf53_pwm_duty(priv,
(info->channels[i].channel - 1),
info->channels[i].duty);
}
break;
}
#else
ret = nrf53_pwm_duty(priv, priv->channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
/* Set output if channel configured */
if (info->channels[i].channel != 0)
{
ret = nrf53_pwm_duty(priv,
(info->channels[i].channel - 1),
info->channels[i].duty);
}
}
/* Start sequence 0 */

9
arch/arm/src/ra4/ra_pwm.c
View file

@ -556,13 +556,14 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
}
/* Calculate the duty cycle register value.
* info->duty is a 16-bit value (0..65535). To avoid 64-bit math we
* can split the 32-bit period into high and low 16-bit parts
* info->channels[0].duty is a 16-bit value (0..65535).
* To avoid 64-bit math we can split the 32-bit period into high
* and low 16-bit parts
*/
hi = period >> 16;
lo = period & 0xffff;
duty16 = (uint32_t)info->duty;
duty16 = (uint32_t)info->channels[0].duty;
duty = hi * duty16;
@ -578,7 +579,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
/* Save the frequency and duty cycle settings */
priv->frequency = info->frequency;
priv->duty = info->duty;
priv->duty = info->channels[0].duty;
/* Stop the timer */

9
arch/arm/src/s32k1xx/s32k1xx_pwm.c
View file

@ -360,10 +360,11 @@ static int pwm_timer(struct s32k1xx_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
pwminfo("FTM%d channel: %d frequency: %" PRId32 " duty: %08" PRIx32 "\n",
priv->tpmid, priv->channel, info->frequency, info->duty);
priv->tpmid, priv->channel, info->frequency,
info->channels[0].duty);
DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
info->duty < uitoub16(100));
DEBUGASSERT(info->frequency > 0 && info->channels[0].duty > 0 &&
info->channels[0].duty < uitoub16(100));
/* Calculate optimal values for the timer prescaler and for the timer
* modulo register. If' frequency' is the desired frequency, then
@ -427,7 +428,7 @@ static int pwm_timer(struct s32k1xx_pwmtimer_s *priv,
* duty cycle = cv / modulo (fractional value)
*/
cv = b16toi(info->duty * modulo + b16HALF);
cv = b16toi(info->channels[0].duty * modulo + b16HALF);
pwminfo("FTM%d PCLK: %" PRId32 " frequency: %" PRId32 " FTMCLK: %" PRId32
" prescaler: %d modulo: %" PRId32 "c0v: %" PRId32 "\n",

2
arch/arm/src/sama5/sam_pwm.c
View file

@ -1022,7 +1022,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
* to the CTDY (vs. the CTDYUPD) register.
*/
regval = b16toi(info->duty * cprd + b16HALF);
regval = b16toi(info->channels[0].duty * cprd + b16HALF);
if (regval > cprd)
{
/* Rounding up could cause the duty value to exceed CPRD (?) */

3
arch/arm/src/samv7/Kconfig
View file

@ -387,7 +387,6 @@ config SAMV7_HAVE_MEDIALB
config SAMV7_PWM
bool
default n
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_PWM_OVERWRITE
select ARCH_HAVE_PWM_DEADTIME
@ -742,7 +741,6 @@ if SAMV7_PWM0
config SAMV7_PWM0_SYNC
bool "PWM0 synchronous channels"
depends on PWM_MULTICHAN
default n
---help---
This option makes the synchronization between channels possible.
@ -1097,7 +1095,6 @@ if SAMV7_PWM1
config SAMV7_PWM1_SYNC
bool "PWM1 synchronous channels"
depends on PWM_MULTICHAN
default n
---help---
This option makes the synchronization between channels possible.

18
arch/arm/src/samv7/sam_pwm.c
View file

@ -963,7 +963,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
const struct pwm_info_s *info)
{
struct sam_pwm_s *priv = (struct sam_pwm_s *)dev;
#ifdef CONFIG_PWM_MULTICHAN
uint32_t regval;
for (int i = 0; i < PWM_NCHANNELS; i++)
@ -1036,18 +1035,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
pwm_putreg(priv, SAMV7_PWM_ENA, CHID_SEL(1));
pwm_putreg(priv, SAMV7_PWM_SCUC, regval);
}
#else
/* Set the frequency and enable PWM output just for first channel */
pwm_set_freq(dev, priv->channels[0].channel, info->frequency);
#ifdef CONFIG_PWM_DEADTIME
pwm_set_deadtime(dev, priv->channels[0].channel,
info->dead_time_a, info->dead_time_b);
#endif
pwm_set_polarity(dev, priv->channels[0].channel,
info->cpol, info->dcpol);
pwm_set_output(dev, priv->channels[0].channel, info->duty);
#endif
pwm_set_comparison(dev);
@ -1078,7 +1065,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev)
struct sam_pwm_s *priv = (struct sam_pwm_s *)dev;
uint32_t regval;
#ifdef CONFIG_PWM_MULTICHAN
for (int i = 0; i < priv->channels_num; i++)
{
regval = CHID_SEL(1 << priv->channels[i].channel);
@ -1091,10 +1077,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev)
regval &= ~(CHID_SEL(1 << 0) | CHID_SEL(1 << 1) |
CHID_SEL(1 << 2) | CHID_SEL(1 << 3));
pwm_putreg(priv, SAMV7_PWM_SCM, regval);
#else
regval = CHID_SEL(1 << priv->channels[0].channel);
pwm_putreg(priv, SAMV7_PWM_DIS, regval);
#endif /* CONFIG_PWM_MULTICHAN */
return OK;
}

1
arch/arm/src/stm32/Kconfig
View file

@ -6034,7 +6034,6 @@ config STM32_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

56
arch/arm/src/stm32/stm32_pwm.c
View file

@ -2321,11 +2321,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel,
pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n",
priv->timid, channel, duty);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(channel == priv->channels[0].channel);
DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
#endif
/* Get the reload values */
reload = pwm_arr_get(dev);
@ -3372,13 +3367,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
pwminfo("TIM%u channel: %u frequency: %" PRIx32 " duty: %08" PRIx32
" count: %" PRIx32 "\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
DEBUGASSERT(info->frequency > 0);
/* Channel specific setup */
duty = info->duty;
duty = info->channels[0].duty;
channel = priv->channels[0].channel;
/* Disable all interrupts and DMA requests, clear all pending status */
@ -3407,7 +3402,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* assured us that the count value is within range).
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Save the remaining count and the number of counts that will have
* elapsed on the first interrupt.
@ -3418,7 +3413,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* value.
*/
priv->prev = pwm_pulsecount(info->count);
priv->prev = pwm_pulsecount(info->channels[0].count);
pwm_rcr_update(dev, priv->prev - 1);
/* Generate an update event to reload the prescaler. This should
@ -3431,8 +3426,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* update event.
*/
priv->count = info->count;
priv->curr = pwm_pulsecount(info->count - priv->prev);
priv->count = info->channels[0].count;
priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev);
pwm_rcr_update(dev, priv->curr - 1);
}
@ -3461,12 +3456,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
goto errout;
}
/* Setup update interrupt. If info->count is > 0, then we can be
* assured that pwm_pulsecount_start() has already verified: (1) that this
* is an advanced timer, and that (2) the repetition count is within range.
/* Setup update interrupt. If info->channels[0].count is > 0, then we can
* be assured that pwm_pulsecount_start() has already verified: (1) that
* this is an advanced timer, and that (2) the repetition count is within
* range.
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Clear all pending interrupts and enable the update interrupt. */
@ -3620,16 +3616,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
uint8_t channel = 0;
ub16_t duty = 0;
int ret = OK;
#ifdef CONFIG_PWM_MULTICHAN
int i = 0;
int j = 0;
#endif
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
#endif
{
#ifdef CONFIG_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -3662,10 +3653,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
ret = -EINVAL;
goto errout;
}
#else
duty = info->duty;
channel = priv->channels[0].channel;
#endif
/* Update duty cycle */
@ -3674,9 +3661,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
{
goto errout;
}
#ifdef CONFIG_PWM_MULTICHAN
}
#endif
}
errout:
@ -3707,19 +3692,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_PWM_MULTICHAN)
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#else
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n",
priv->timid, priv->channels[0].channel,
info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* TODO: what if we have pwm running and we want disable some channels ? */
@ -4336,14 +4312,14 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev,
/* Generate an indefinite number of pulses */
if (info->count == 0)
if (info->channels[0].count == 0)
{
return pwm_start(dev, info);
}
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting)
* REVISIT: verify if TIMTYPE_COUNTUP16_N works with it
@ -4352,7 +4328,7 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev,
if (priv->timtype != TIMTYPE_ADVANCED)
{
pwmerr("ERROR: TIM%u cannot support pulse count: %" PRIx32 "\n",
priv->timid, info->count);
priv->timid, info->channels[0].count);
return -EPERM;
}
}
@ -4377,7 +4353,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (info->frequency == priv->frequency)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
@ -4397,9 +4372,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
}
#else
ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
}
else
{

2
arch/arm/src/stm32/stm32_pwm.h
View file

@ -356,7 +356,7 @@
#endif
#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
#else /* !CONFIG_PWM_MULTICHAN */
#else /* !CONFIG_STM32_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:

1
arch/arm/src/stm32f0l0g0/Kconfig
View file

@ -3126,7 +3126,6 @@ config STM32F0L0G0_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32F0L0G0_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output channels per timer.

59
arch/arm/src/stm32f0l0g0/stm32_pwm.c
View file

@ -852,9 +852,7 @@ static int stm32pwm_output_configure(struct stm32_pwmtimer_s *priv,
static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
const struct pwm_info_s *info)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
#endif
/* Calculated values */
@ -884,24 +882,17 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
ccmr2 = stm32pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
#endif
#if defined(CONFIG_PWM_MULTICHAN)
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#elif defined(CONFIG_PWM_PULSECOUNT)
#ifdef CONFIG_PWM_PULSECOUNT
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32
" count: %u\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
#else
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty);
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* Disable all interrupts and DMA requests, clear all pending status */
@ -1080,7 +1071,7 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
*/
#ifdef CONFIG_PWM_PULSECOUNT
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Save the remaining count and the number of counts that will have
* elapsed on the first interrupt.
@ -1091,7 +1082,7 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
* value.
*/
priv->prev = stm32pwm_pulsecount(info->count);
priv->prev = stm32pwm_pulsecount(info->channels[0].count);
stm32pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->prev - 1);
/* Generate an update event to reload the prescaler. This should
@ -1104,8 +1095,9 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
* update event.
*/
priv->count = info->count;
priv->curr = stm32pwm_pulsecount(info->count - priv->prev);
priv->count = info->channels[0].count;
priv->curr = stm32pwm_pulsecount(info->channels[0].count
- priv->prev);
stm32pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1);
}
@ -1138,20 +1130,15 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
ocmode2 = 0;
#endif
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
#endif
{
ub16_t duty;
uint32_t chanmode;
bool ocmbit = false;
uint8_t channel;
#ifdef CONFIG_PWM_MULTICHAN
int j;
#endif
enum stm32_chanmode_e mode;
#ifdef CONFIG_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -1185,11 +1172,6 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
pwmerr("ERROR: No such channel: %u\n", channel);
return -EINVAL;
}
#else
duty = info->duty;
channel = priv->channels[0].channel;
mode = priv->channels[0].mode;
#endif
/* Duty cycle:
*
@ -1399,13 +1381,14 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
cr1 |= GTIM_CR1_ARPE;
stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
/* Setup update interrupt. If info->count is > 0, then we can be
* assured that stm32pwm_start() has already verified: (1) that this is an
* advanced timer, and that (2) the repetition count is within range.
/* Setup update interrupt. If info->channels[0].count is > 0, then we can
* be assured that stm32pwm_start() has already verified: (1) that this
* is an advanced timer, and that (2) the repetition count is within
* range.
*/
#ifdef CONFIG_PWM_PULSECOUNT
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Clear all pending interrupts and enable the update interrupt. */
@ -1468,11 +1451,6 @@ static int stm32pwm_update_duty(struct stm32_pwmtimer_s *priv,
pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n",
priv->timid, channel, duty);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(channel == priv->channels[0].channel);
DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
#endif
/* Get the reload values */
reload = stm32pwm_getreg(priv, STM32_GTIM_ARR_OFFSET);
@ -1913,14 +1891,14 @@ static int stm32pwm_start(struct pwm_lowerhalf_s *dev,
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting) */
if (priv->timtype != TIMTYPE_ADVANCED)
{
pwmerr("ERROR: TIM%u cannot support pulse count: %u\n",
priv->timid, info->count);
priv->timid, info->channels[0].count);
return -EPERM;
}
}
@ -1945,7 +1923,6 @@ static int stm32pwm_start(struct pwm_lowerhalf_s *dev,
if (info->frequency == priv->frequency)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
@ -1965,10 +1942,6 @@ static int stm32pwm_start(struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
}
#else
ret = stm32pwm_update_duty(priv, priv->channels[0].channel,
info->duty);
#endif
}
else
#endif

153
arch/arm/src/stm32f0l0g0/stm32_pwm.h
View file

@ -105,8 +105,6 @@
defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM17_PWM)
#ifdef CONFIG_PWM_MULTICHAN
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
@ -337,157 +335,6 @@
MAX(PWM_TIM16_NCHANNELS, \
PWM_TIM17_NCHANNELS))))))
#else /* !CONFIG_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:
*
* CONFIG_STM32F0L0G0_TIMx_CHANNEL - Specifies the timer output channel
* {1,..,4} PWM_TIMx_CHn - One of the values defined in
* chip/stm32*_pinmap.h. In the case where there are multiple pin
* selections, the correct setting must be provided in the arch/board/board.h
* file.
*
* NOTE: The STM32 timers are each capable of generating different signals on
* each of the four channels with different duty cycles. That capability is
* not supported by this driver: Only one output channel per timer.
*/
#ifdef CONFIG_STM32F0L0G0_TIM1_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM1_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM1_CH1MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# define PWM_TIM1_CH1NCFG 0
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM1_CH2MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# define PWM_TIM1_CH2NCFG 0
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 3
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL3 1
# define CONFIG_STM32F0L0G0_TIM1_CH3MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# define PWM_TIM1_CH3NCFG 0
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 4
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL4 1
# define CONFIG_STM32F0L0G0_TIM1_CH4MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM1_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM2_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM2_CH1MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM2_CH2MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 3
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL3 1
# define CONFIG_STM32F0L0G0_TIM2_CH3MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 4
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL4 1
# define CONFIG_STM32F0L0G0_TIM2_CH4MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM2_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM3_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM3_CH1MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM3_CH2MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 3
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL3 1
# define CONFIG_STM32F0L0G0_TIM3_CH3MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 4
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL4 1
# define CONFIG_STM32F0L0G0_TIM3_CH4MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM3_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM14_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM14_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM14_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM14_CH1MODE CONFIG_STM32F0L0G0_TIM14_CHMODE
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# define PWM_TIM14_CH1NCFG 0
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM14_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM15_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM15_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM15_CH1MODE CONFIG_STM32F0L0G0_TIM15_CHMODE
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# define PWM_TIM15_CH1NCFG 0
# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM15_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM15_CH2MODE CONFIG_STM32F0L0G0_TIM15_CHMODE
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM15_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM16_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM16_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM16_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM16_CH1MODE CONFIG_STM32F0L0G0_TIM16_CHMODE
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# define PWM_TIM16_CH1NCFG 0
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM16_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM17_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM17_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM17_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM17_CH1MODE CONFIG_STM32F0L0G0_TIM17_CHMODE
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# define PWM_TIM17_CH1NCFG 0
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM17_CHANNEL"
# endif
#endif
#define PWM_NCHANNELS 1
#endif
/* Complementary outputs support */
#if defined(CONFIG_STM32F0L0G0_TIM1_CH1NOUT) || defined(CONFIG_STM32F0L0G0_TIM1_CH2NOUT) || \

1
arch/arm/src/stm32f7/Kconfig
View file

@ -4658,7 +4658,6 @@ config STM32F7_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32F7_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

56
arch/arm/src/stm32f7/stm32_pwm.c
View file

@ -1926,11 +1926,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel,
pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n",
priv->timid, channel, duty);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(channel == priv->channels[0].channel);
DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
#endif
/* Get the reload values */
reload = pwm_arr_get(dev);
@ -2948,13 +2943,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
pwminfo("TIM%u channel: %u frequency: %" PRIx32 " duty: %08" PRIx32
" count: %" PRIx32 "\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
DEBUGASSERT(info->frequency > 0);
/* Channel specific setup */
duty = info->duty;
duty = info->channels[0].duty;
channel = priv->channels[0].channel;
/* Disable all interrupts and DMA requests, clear all pending status */
@ -2983,7 +2978,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* assured us that the count value is within range).
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Save the remaining count and the number of counts that will have
* elapsed on the first interrupt.
@ -2994,7 +2989,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* value.
*/
priv->prev = pwm_pulsecount(info->count);
priv->prev = pwm_pulsecount(info->channels[0].count);
pwm_rcr_update(dev, priv->prev - 1);
/* Generate an update event to reload the prescaler. This should
@ -3007,8 +3002,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* update event.
*/
priv->count = info->count;
priv->curr = pwm_pulsecount(info->count - priv->prev);
priv->count = info->channels[0].count;
priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev);
pwm_rcr_update(dev, priv->curr - 1);
}
@ -3037,12 +3032,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
goto errout;
}
/* Setup update interrupt. If info->count is > 0, then we can be
* assured that pwm_pulsecount_start() has already verified: (1) that this
* is an advanced timer, and that (2) the repetition count is within range.
/* Setup update interrupt. If info->channels[0].count is > 0, then we can
* be assured that pwm_pulsecount_start() has already verified: (1) that
* this is an advanced timer, and that (2) the repetition count is within
* range.
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Clear all pending interrupts and enable the update interrupt. */
@ -3194,16 +3190,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
uint8_t channel = 0;
ub16_t duty = 0;
int ret = OK;
#ifdef CONFIG_PWM_MULTICHAN
int i = 0;
int j = 0;
#endif
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
#endif
{
#ifdef CONFIG_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -3236,10 +3227,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
ret = -EINVAL;
goto errout;
}
#else
duty = info->duty;
channel = priv->channels[0].channel;
#endif
/* Update duty cycle */
@ -3248,9 +3235,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
{
goto errout;
}
#ifdef CONFIG_PWM_MULTICHAN
}
#endif
}
errout:
@ -3281,19 +3266,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_PWM_MULTICHAN)
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#else
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n",
priv->timid, priv->channels[0].channel,
info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* TODO: what if we have pwm running and we want disable some channels ? */
@ -3882,21 +3858,21 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev,
/* Generate an indefinite number of pulses */
if (info->count == 0)
if (info->channels[0].count == 0)
{
return pwm_start(dev, info);
}
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting) */
if (priv->timtype != TIMTYPE_ADVANCED)
{
pwmerr("ERROR: TIM%u cannot support pulse count: %" PRIx32 "\n",
priv->timid, info->count);
priv->timid, info->channels[0].count);
return -EPERM;
}
}
@ -3921,7 +3897,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (info->frequency == priv->frequency)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
@ -3941,9 +3916,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
}
#else
ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
}
else
{

2
arch/arm/src/stm32f7/stm32_pwm.h
View file

@ -321,7 +321,7 @@
#endif
#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1)
#else /* !CONFIG_PWM_MULTICHAN */
#else /* !CONFIG_STM32F7_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:

1
arch/arm/src/stm32h5/Kconfig
View file

@ -3373,7 +3373,6 @@ config STM32H5_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32H5_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

54
arch/arm/src/stm32h5/stm32_pwm.c
View file

@ -1991,11 +1991,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel,
pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n",
priv->timid, channel, duty);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(channel == priv->channels[0].channel);
DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
#endif
/* Get the reload values */
reload = pwm_arr_get(dev);
@ -3043,13 +3038,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
DEBUGASSERT(info->frequency > 0);
/* Channel specific setup */
duty = info->duty;
duty = info->channels[0].duty;
channel = priv->channels[0].channel;
mode = priv->channels[0].mode;
@ -3079,7 +3074,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* assured us that the count value is within range).
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Save the remaining count and the number of counts that will have
* elapsed on the first interrupt.
@ -3090,7 +3085,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* value.
*/
priv->prev = pwm_pulsecount(info->count);
priv->prev = pwm_pulsecount(info->channels[0].count);
pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1);
/* Generate an update event to reload the prescaler. This should
@ -3103,8 +3098,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* update event.
*/
priv->count = info->count;
priv->curr = pwm_pulsecount(info->count - priv->prev);
priv->count = info->channels[0].count;
priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev);
pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
}
@ -3133,12 +3128,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
goto errout;
}
/* Setup update interrupt. If info->count is > 0, then we can be
* assured that pwm_pulsecount_start() has already verified: (1) that this
* is an advanced timer, and that (2) the repetition count is within range.
/* Setup update interrupt. If info->channels[0].count is > 0, then we can
* be assured that pwm_pulsecount_start() has already verified: (1) that
* this is an advanced timer, and that (2) the repetition count is within
* range.
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Clear all pending interrupts and enable the update interrupt. */
@ -3292,16 +3288,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
uint8_t channel = 0;
ub16_t duty = 0;
int ret = OK;
#ifdef CONFIG_PWM_MULTICHAN
int i = 0;
int j = 0;
#endif
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
#endif
{
#ifdef CONFIG_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -3334,10 +3325,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
ret = -EINVAL;
goto errout;
}
#else
duty = info->duty;
channel = priv->channels[0].channel;
#endif
/* Update duty cycle */
@ -3346,9 +3333,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
{
goto errout;
}
#ifdef CONFIG_PWM_MULTICHAN
}
#endif
}
errout:
@ -3379,19 +3364,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_PWM_MULTICHAN)
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#else
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n",
priv->timid, priv->channels[0].channel,
info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* TODO: what if we have pwm running and we want disable some channels ? */
@ -3976,7 +3952,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting)
* REVISIT: verify if TIMTYPE_COUNTUP16_N works with it
@ -3985,7 +3961,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (priv->timtype != TIMTYPE_ADVANCED)
{
pwmerr("ERROR: TIM%u cannot support pulse count: %u\n",
priv->timid, info->count);
priv->timid, info->channels[0].count);
return -EPERM;
}
}
@ -4009,7 +3985,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (info->frequency == priv->frequency)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
@ -4029,9 +4004,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
}
#else
ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
}
else
{

2
arch/arm/src/stm32h5/stm32_pwm.h
View file

@ -321,7 +321,7 @@
#endif
#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
#else /* !CONFIG_PWM_MULTICHAN */
#else /* !CONFIG_STM32H5_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:

1
arch/arm/src/stm32h7/Kconfig
View file

@ -4312,7 +4312,6 @@ config STM32H7_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32H7_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

54
arch/arm/src/stm32h7/stm32_pwm.c
View file

@ -1995,11 +1995,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel,
pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n",
priv->timid, channel, duty);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(channel == priv->channels[0].channel);
DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
#endif
/* Get the reload values */
reload = pwm_arr_get(dev);
@ -3047,13 +3042,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
DEBUGASSERT(info->frequency > 0);
/* Channel specific setup */
duty = info->duty;
duty = info->channels[0].duty;
channel = priv->channels[0].channel;
mode = priv->channels[0].mode;
@ -3083,7 +3078,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* assured us that the count value is within range).
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Save the remaining count and the number of counts that will have
* elapsed on the first interrupt.
@ -3094,7 +3089,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* value.
*/
priv->prev = pwm_pulsecount(info->count);
priv->prev = pwm_pulsecount(info->channels[0].count);
pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1);
/* Generate an update event to reload the prescaler. This should
@ -3107,8 +3102,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* update event.
*/
priv->count = info->count;
priv->curr = pwm_pulsecount(info->count - priv->prev);
priv->count = info->channels[0].count;
priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev);
pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
}
@ -3137,12 +3132,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
goto errout;
}
/* Setup update interrupt. If info->count is > 0, then we can be
* assured that pwm_pulsecount_start() has already verified: (1) that this
* is an advanced timer, and that (2) the repetition count is within range.
/* Setup update interrupt. If info->channels[0].count is > 0, then we can
* be assured that pwm_pulsecount_start() has already verified: (1) that
* this is an advanced timer, and that (2) the repetition count is within
* range.
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Clear all pending interrupts and enable the update interrupt. */
@ -3296,16 +3292,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
uint8_t channel = 0;
ub16_t duty = 0;
int ret = OK;
#ifdef CONFIG_PWM_MULTICHAN
int i = 0;
int j = 0;
#endif
#ifdef CONFIG_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
#endif
{
#ifdef CONFIG_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -3338,10 +3329,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
ret = -EINVAL;
goto errout;
}
#else
duty = info->duty;
channel = priv->channels[0].channel;
#endif
/* Update duty cycle */
@ -3350,9 +3337,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
{
goto errout;
}
#ifdef CONFIG_PWM_MULTICHAN
}
#endif
}
errout:
@ -3383,19 +3368,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_PWM_MULTICHAN)
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#else
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n",
priv->timid, priv->channels[0].channel,
info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* TODO: what if we have pwm running and we want disable some channels ? */
@ -3980,7 +3956,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting)
* REVISIT: verify if TIMTYPE_COUNTUP16_N works with it
@ -3989,7 +3965,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (priv->timtype != TIMTYPE_ADVANCED)
{
pwmerr("ERROR: TIM%u cannot support pulse count: %u\n",
priv->timid, info->count);
priv->timid, info->channels[0].count);
return -EPERM;
}
}
@ -4013,7 +3989,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (info->frequency == priv->frequency)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
@ -4033,9 +4008,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
}
#else
ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
}
else
{

2
arch/arm/src/stm32h7/stm32_pwm.h
View file

@ -321,7 +321,7 @@
#endif
#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
#else /* !CONFIG_PWM_MULTICHAN */
#else /* !CONFIG_STM32H7_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:

1
arch/arm/src/stm32l4/Kconfig
View file

@ -3709,7 +3709,6 @@ config STM32L4_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32L4_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

67
arch/arm/src/stm32l4/stm32l4_pwm.c
View file

@ -1806,11 +1806,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel,
pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n",
priv->timid, channel, duty);
#ifndef CONFIG_STM32L4_PWM_MULTICHAN
DEBUGASSERT(channel == priv->channels[0].channel);
DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
#endif
/* Get the reload values */
reload = pwm_arr_get(dev);
@ -2945,13 +2940,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n",
priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
info->channels[0].duty, info->channels[0].count);
DEBUGASSERT(info->frequency > 0);
/* Channel specific setup */
duty = info->duty;
duty = info->channels[0].duty;
channel = priv->channels[0].channel;
/* Disable all interrupts and DMA requests, clear all pending status */
@ -2980,7 +2975,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* assured us that the count value is within range).
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Save the remaining count and the number of counts that will have
* elapsed on the first interrupt.
@ -2991,7 +2986,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* value.
*/
priv->prev = pwm_pulsecount(info->count);
priv->prev = pwm_pulsecount(info->channels[0].count);
pwm_putreg(priv, STM32L4_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1);
/* Generate an update event to reload the prescaler. This should
@ -3004,8 +2999,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
* update event.
*/
priv->count = info->count;
priv->curr = pwm_pulsecount(info->count - priv->prev);
priv->count = info->channels[0].count;
priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev);
pwm_putreg(priv, STM32L4_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
}
@ -3034,12 +3029,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev,
goto errout;
}
/* Setup update interrupt. If info->count is > 0, then we can be
* assured that pwm_pulsecount_start() has already verified: (1) that this
* is an advanced timer, and that (2) the repetition count is within range.
/* Setup update interrupt. If info->channels[0].count is > 0, then we can
* be assured that pwm_pulsecount_start() has already verified: (1) that
* this is an advanced timer, and that (2) the repetition count is within
* range.
*/
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Clear all pending interrupts and enable the update interrupt. */
@ -3078,16 +3074,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
uint8_t channel = 0;
ub16_t duty = 0;
int ret = OK;
#ifdef CONFIG_STM32L4_PWM_MULTICHAN
int i = 0;
int j = 0;
#endif
#ifdef CONFIG_STM32L4_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
#endif
{
#ifdef CONFIG_STM32L4_PWM_MULTICHAN
/* Break the loop if all following channels are not configured */
if (info->channels[i].channel == -1)
@ -3120,10 +3111,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
ret = -EINVAL;
goto errout;
}
#else
duty = info->duty;
channel = priv->channels[0].channel;
#endif
/* Update duty cycle */
@ -3132,9 +3119,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev,
{
goto errout;
}
#ifdef CONFIG_STM32L4_PWM_MULTICHAN
}
#endif
}
errout:
@ -3165,19 +3150,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_STM32L4_PWM_MULTICHAN)
pwminfo("TIM%u frequency: %" PRIu32 "\n",
priv->timid, info->frequency);
#else
pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n",
priv->timid, priv->channels[0].channel,
info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_STM32L4_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* TODO: what if we have pwm running and we want disable some channels ? */
@ -3272,19 +3248,10 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_STM32L4_PWM_MULTICHAN)
pwminfo("LPTIM%u frequency: %u\n",
priv->timid, info->frequency);
#else
pwminfo("LPTIM%u channel: %u frequency: %u duty: %08x\n",
priv->timid, priv->channels[0].channel,
info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
#ifndef CONFIG_STM32L4_PWM_MULTICHAN
DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
#endif
/* Enable again, ARR and CMP need to be written while enabled */
@ -3298,11 +3265,7 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev,
goto errout;
}
#ifdef CONFIG_STM32L4_PWM_MULTICHAN
ub16_t duty = info->channels[0].duty;
#else
ub16_t duty = info->duty;
#endif
/* Update duty cycle */
@ -3883,14 +3846,14 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting) */
if (priv->timtype != TIMTYPE_ADVANCED)
{
pwmerr("ERROR: TIM%u cannot support pulse count: %u\n",
priv->timid, info->count);
priv->timid, info->channels[0].count);
return -EPERM;
}
}
@ -3915,7 +3878,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
if (info->frequency == priv->frequency)
{
#ifdef CONFIG_STM32L4_PWM_MULTICHAN
int i;
for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
@ -3935,9 +3897,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
}
#else
ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
#endif /* CONFIG_STM32L4_PWM_MULTICHAN */
}
else
{

1
arch/arm/src/stm32l5/Kconfig
View file

@ -1700,7 +1700,6 @@ config STM32L5_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32L5_TIM1_PWM || STM32L5_TIM2_PWM || STM32L5_TIM3_PWM || STM32L5_TIM4_PWM || STM32L5_TIM5_PWM || STM32L5_TIM8_PWM || STM32L5_TIM15_PWM || STM32L5_TIM16_PWM || STM32L5_TIM17_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

1
arch/arm/src/stm32u5/Kconfig
View file

@ -1998,7 +1998,6 @@ config STM32U5_PWM_MULTICHAN
bool "PWM Multiple Output Channels"
default n
depends on STM32U5_PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Specifies that the PWM driver supports multiple output
channels per timer.

8
arch/arm/src/tiva/common/tiva_pwm.c
View file

@ -568,8 +568,8 @@ static int tiva_pwm_start(struct pwm_lowerhalf_s *dev,
* Count should be add 1 for the first time
*/
chan->count = info->count;
chan->cur_count = info->count;
chan->count = info->channels[0].count;
chan->cur_count = info->channels[0].count;
if (!chan->inited)
{
@ -580,7 +580,7 @@ static int tiva_pwm_start(struct pwm_lowerhalf_s *dev,
/* Count 0 means to generate indefinite number of pulses */
if (info->count == 0)
if (info->channels[0].count == 0)
{
pwm_expired(chan->handle);
@ -636,7 +636,7 @@ static int tiva_pwm_start(struct pwm_lowerhalf_s *dev,
static inline int tiva_pwm_timer(struct tiva_pwm_chan_s *chan,
const struct pwm_info_s *info)
{
uint16_t duty = info->duty;
uint16_t duty = info->channels[0].duty;
uint32_t frequency = info->frequency;
pwminfo("> frequency = %d\n", frequency);

21
arch/arm/src/tlsr82/tlsr82_pwm.c
View file

@ -308,12 +308,12 @@ static int pwm_config(struct tlsr82_pwmtimer_s *priv,
pwminfo("PWM%d invert: %d frequency: %lu duty: %08lx\n",
(int)priv->id, (int)priv->invert, info->frequency,
info->duty);
info->channels[0].duty);
if (info->frequency == 0 || info->duty >= uitoub16(100))
if (info->frequency == 0 || info->channels[0].duty >= uitoub16(100))
{
pwrerr("pwm info is invalid, fre: %lu duty: %08lx\n",
info->frequency, info->duty);
info->frequency, info->channels[0].duty);
return -EINVAL;
}
@ -331,10 +331,11 @@ static int pwm_config(struct tlsr82_pwmtimer_s *priv,
max = (uint16_t)((g_pwmclk / info->frequency));
cmp = (uint16_t)(((uint64_t)max * (uint64_t)info->duty) >> 16);
cmp = (uint16_t)(((uint64_t)max * (uint64_t)info->channels[0].duty) >> 16);
pwminfo("PWM%d PCLK: %lu freq: %lu duty: %lu max: %u cmp: %u\n",
priv->id, g_pwmclk, info->frequency, info->duty, max, cmp);
priv->id, g_pwmclk, info->frequency, info->channels[0].duty,
max, cmp);
priv->max = max;
priv->cmp = cmp;
@ -616,25 +617,25 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
/* Check if a pulsecount has been selected */
if (info->count > 0)
if (info->channels[0].count > 0)
{
/* Only the PWM0 support the pulse counting */
if (priv->id != 0)
{
pwmerr("ERROR: PWM%d cannot support pulse count: %lu\n",
priv->id, info->count);
priv->id, info->channels[0].count);
return -EPERM;
}
if (info->count > PWM_MAX_COUNT)
if (info->channels[0].count > PWM_MAX_COUNT)
{
pwmerr("ERROR: PWM0 count out of range, count: %lu, max: %d",
info->count, PWM_MAX_COUNT);
info->channels[0].count, PWM_MAX_COUNT);
return -EINVAL;
}
priv->count = info->count;
priv->count = info->channels[0].count;
}
/* Save the handle */

14
arch/arm/src/xmc4/xmc4_pwm.c
View file

@ -851,7 +851,7 @@ static int pwm_compute_config(struct xmc4_pwm_s *priv,
uint32_t crs = 0;
uint32_t f_pwm = info->frequency;
float duty_cycle = (1.0 - b16tof(info->duty));
float duty_cycle = (1.0 - b16tof(info->channels[0].duty));
do
{
@ -919,7 +919,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info)
pwm_set_period_match(priv, prs);
pwm_set_compare_match(priv, crs);
pwm_set_passive_level(priv, info->cpol);
pwm_set_passive_level(priv, info->channels[0].cpol);
pwm_shadow_transfert(priv);
}
else
@ -933,7 +933,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info)
pwm_set_compare_match(priv, crs);
pwm_set_period_match(priv, prs);
pwm_set_passive_level(priv, info->cpol);
pwm_set_passive_level(priv, info->channels[0].cpol);
pwm_shadow_transfert(priv);
pwm_enable_slice_clock(priv);
@ -948,7 +948,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info)
pwm_set_compare_match(priv, crs);
pwm_set_period_match(priv, prs);
pwm_set_passive_level(priv, info->cpol);
pwm_set_passive_level(priv, info->channels[0].cpol);
pwm_shadow_transfert(priv);
pwm_enable_slice_clock(priv);
@ -956,17 +956,17 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info)
}
priv->frequency = info->frequency;
priv->duty = info->duty;
priv->duty = info->channels[0].duty;
}
else
{
/* Frequency doesn't change, update shadow transfer */
pwm_set_compare_match(priv, crs);
pwm_set_passive_level(priv, info->cpol);
pwm_set_passive_level(priv, info->channels[0].cpol);
pwm_shadow_transfert(priv);
priv->duty = info->duty;
priv->duty = info->channels[0].duty;
}
return OK;

3
arch/arm64/src/imx9/Kconfig
View file

@ -17,7 +17,6 @@ config ARCH_CHIP_IMX93
select ARMV8A_HAVE_GICv3
select ARCH_CORTEX_A55 if !IMX9_BOOTLOADER
select ARCH_CORTEX_A53 if IMX9_BOOTLOADER
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_RESET
---help---
EL3/OCRAM is a bad combination for atomic instructions, they don't work.
@ -67,7 +66,6 @@ endmenu # DMA Allocator Configuration
config IMX9_FLEXIO_PWM
bool
select PWM_MULTICHAN
default n
config IMX9_HAVE_ATF_FIRMWARE
@ -445,7 +443,6 @@ config IMX9_FLEXIO2_DSHOT_TX_TIMER
config IMX9_TPM_PWM
bool
select PWM_MULTICHAN
default n
config IMX9_TPM1_PWM

2
arch/risc-v/Kconfig
View file

@ -261,7 +261,6 @@ config ARCH_CHIP_MPFS
select ARCH_HAVE_ELF_EXECUTABLE
select ARCH_HAVE_RESET
select ARCH_HAVE_SPI_CS_CONTROL
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_S_MODE
select ARCH_RV_CPUID_MAP
select ARCH_HAVE_PERF_EVENTS
@ -447,7 +446,6 @@ config ARCH_CHIP_RP23XX_RV
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_RESET
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET

1
arch/risc-v/src/bl602/Kconfig
View file

@ -18,7 +18,6 @@ config BL602_HAVE_UART0
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_HAVE_PWM_MULTICHAN
config BL602_UART0
bool

2
arch/risc-v/src/bl602/bl602_pwm_lowerhalf.c
View file

@ -387,7 +387,7 @@ static int bl602_pwm_start(struct pwm_lowerhalf_s *dev,
}
#else
bl602_pwm_freq(priv, 0, info->frequency);
bl602_pwm_duty(priv, 0, info->duty);
bl602_pwm_duty(priv, 0, info->channels[0].duty);
pwm_channel_enable(0);
#endif

21
arch/risc-v/src/common/espressif/Kconfig
View file

@ -1671,7 +1671,6 @@ config ESPRESSIF_LEDC
bool "LEDC (PWM)"
default n
select PWM
select ARCH_HAVE_PWM_MULTICHAN
config ESPRESSIF_SHA_ACCELERATOR
bool "SHA Accelerator"
@ -3677,8 +3676,8 @@ if ESPRESSIF_LEDC_TIMER0
config ESPRESSIF_LEDC_TIMER0_CHANNELS
int "Number of Timer 0 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER0_RESOLUTION
@ -3701,8 +3700,8 @@ if ESPRESSIF_LEDC_TIMER1
config ESPRESSIF_LEDC_TIMER1_CHANNELS
int "Number of Timer 1 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER1_RESOLUTION
@ -3725,8 +3724,8 @@ if ESPRESSIF_LEDC_TIMER2
config ESPRESSIF_LEDC_TIMER2_CHANNELS
int "Number of Timer 2 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER2_RESOLUTION
@ -3749,8 +3748,8 @@ if ESPRESSIF_LEDC_TIMER3
config ESPRESSIF_LEDC_TIMER3_CHANNELS
int "Number of Timer 3 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER3_RESOLUTION
@ -3781,7 +3780,7 @@ config ESPRESSIF_LEDC_CHANNEL3_PIN
int "Channel 3 pin"
default 5
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config ESPRESSIF_LEDC_CHANNEL4_PIN
int "Channel 4 pin"
@ -3791,7 +3790,7 @@ config ESPRESSIF_LEDC_CHANNEL5_PIN
int "Channel 5 pin"
default 7
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endmenu # LEDC configuration

1
arch/risc-v/src/esp32c3-legacy/Kconfig
View file

@ -185,7 +185,6 @@ config ESP32C3_LEDC
bool "LEDC (PWM)"
default n
select PWM
select ARCH_HAVE_PWM_MULTICHAN
config ESP32C3_GPIO_IRQ
bool "GPIO pin interrupts"

14
arch/risc-v/src/litex/litex_pwm.c
View file

@ -44,10 +44,11 @@
****************************************************************************/
#ifdef CONFIG_PWM_PULSECOUNT
#error PWM puslecount not supported for Litex.
# error PWM pulsecount not supported for Litex.
#endif
#ifdef CONFIG_PWM_MULTICHAN
#error PWM multichannel not supported for Litex.
#if CONFIG_PWM_NCHANNELS > 1
# error PWM multiple channels not supported for Litex.
#endif
/* Control register offsets from peripheral base address */
@ -219,7 +220,7 @@ static int litex_pwm_start(struct pwm_lowerhalf_s *dev,
const uint32_t min_in_duty = 1;
update_frequency = priv->frequency != info->frequency;
update_duty = update_frequency | (priv->duty != info->duty);
update_duty = update_frequency | (priv->duty != info->channels[0].duty);
DEBUGASSERT(dev);
DEBUGASSERT(priv->base);
@ -260,8 +261,9 @@ static int litex_pwm_start(struct pwm_lowerhalf_s *dev,
*/
period = getreg32(priv->base + PWM_PERIOD_REG_OFFSET);
duty = period * (info->duty / (float)(max_in_duty - min_in_duty));
priv->duty = info->duty;
duty = period * (info->channels[0].duty / (float)(max_in_duty -
min_in_duty));
priv->duty = info->channels[0].duty;
putreg32(duty, priv->base + PWM_WIDTH_REG_OFFSET);
pwminfo("Update PWM duty to %lu\n", duty);

2
arch/risc-v/src/mpfs/Kconfig
View file

@ -609,7 +609,6 @@ config MPFS_HAVE_COREPWM
config MPFS_COREPWM0
bool "CorePWM0 FPGA IP block configured"
default n
select PWM_MULTICHAN
depends on MPFS_HAVE_COREPWM
config MPFS_COREPWM0_BASE
@ -632,7 +631,6 @@ config MPFS_COREPWM0_NCHANNELS
config MPFS_COREPWM1
bool "CorePWM1 FPGA IP block configured"
default n
select PWM_MULTICHAN
depends on MPFS_HAVE_COREPWM
config MPFS_COREPWM1_BASE

21
arch/xtensa/src/common/espressif/Kconfig
View file

@ -195,7 +195,6 @@ config ESPRESSIF_LEDC
default n
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
select PWM
select ARCH_HAVE_PWM_MULTICHAN
config ESPRESSIF_SHA_ACCELERATOR
bool "SHA Accelerator"
@ -340,8 +339,8 @@ if ESPRESSIF_LEDC_TIMER0
config ESPRESSIF_LEDC_TIMER0_CHANNELS
int "Number of Timer 0 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER0_RESOLUTION
@ -363,8 +362,8 @@ if ESPRESSIF_LEDC_TIMER1
config ESPRESSIF_LEDC_TIMER1_CHANNELS
int "Number of Timer 1 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER1_RESOLUTION
@ -386,8 +385,8 @@ if ESPRESSIF_LEDC_TIMER2
config ESPRESSIF_LEDC_TIMER2_CHANNELS
int "Number of Timer 2 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER2_RESOLUTION
@ -409,8 +408,8 @@ if ESPRESSIF_LEDC_TIMER3
config ESPRESSIF_LEDC_TIMER3_CHANNELS
int "Number of Timer 3 channels"
default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1
default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1
default 2 if PWM_NCHANNELS > 1
default 1 if PWM_NCHANNELS = 1
range 0 6
config ESPRESSIF_LEDC_TIMER3_RESOLUTION
@ -450,7 +449,7 @@ config ESPRESSIF_LEDC_CHANNEL3_PIN
range 0 48 if ARCH_CHIP_ESP32S3
range 0 46 if ARCH_CHIP_ESP32S2
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config ESPRESSIF_LEDC_CHANNEL4_PIN
int "Channel 4 pin"
@ -476,7 +475,7 @@ config ESPRESSIF_LEDC_CHANNEL7_PIN
range 0 48 if ARCH_CHIP_ESP32S3
range 0 46 if ARCH_CHIP_ESP32S2
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # !ESP32_LEDC && !ESP32S2_LEDC && !ESP32S3_LEDC

1
arch/xtensa/src/esp32/Kconfig
View file

@ -293,7 +293,6 @@ config ESP32_LEDC
bool "LEDC (PWM)"
default n
select PWM
select ARCH_HAVE_PWM_MULTICHAN
---help---
Enable support to PWM on ESP32 using LEDC peripheral.

1
arch/xtensa/src/esp32s2/Kconfig
View file

@ -544,7 +544,6 @@ config ESP32S2_LEDC
bool "LEDC (PWM)"
default n
select PWM
select ARCH_HAVE_PWM_MULTICHAN
select ESPRESSIF_LEDC
---help---
Enable support to PWM on ESP32S2 using LEDC peripheral.

1
arch/xtensa/src/esp32s3/Kconfig
View file

@ -817,7 +817,6 @@ config ESP32S3_LEDC
bool "LEDC (PWM)"
default n
select PWM
select ARCH_HAVE_PWM_MULTICHAN
select ESPRESSIF_LEDC
---help---
Enable support to PWM on ESP32S3 using LEDC peripheral.

1
boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig
View file

@ -40,7 +40,6 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=2
CONFIG_RAM_SIZE=1048576
CONFIG_RAM_START=0x20200000

1
boards/arm/nrf52/nrf52840-dk/configs/jumbo/defconfig
View file

@ -60,7 +60,6 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=4
CONFIG_RAM_SIZE=65535
CONFIG_RAM_START=0x20000000

1
boards/arm/nrf53/nrf5340-dk/configs/pwm_cpuapp/defconfig
View file

@ -40,7 +40,6 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=4
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20000000

1
boards/arm/nrf53/thingy53/configs/rgbled_cpuapp/defconfig
View file

@ -53,7 +53,6 @@ CONFIG_NSH_READLINE=y
CONFIG_NSH_USBCONSOLE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAMLOG=y
CONFIG_RAM_SIZE=524288

6
boards/arm/nrf53/thingy53/include/board.h
View file

@ -137,14 +137,8 @@
* BLUE - P1.07
*/
#ifdef CONFIG_PWM_MULTICHAN
# define NRF53_PWM0_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(8))
# define NRF53_PWM0_CH1_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(6))
# define NRF53_PWM0_CH2_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(7))
#else
# define NRF53_PWM0_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(8))
# define NRF53_PWM1_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(6))
# define NRF53_PWM2_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(7))
#endif
#endif /* __BOARDS_ARM_NRF53_THINGY53_INCLUDE_BOARD_H */

51
boards/arm/nrf53/thingy53/src/nrf53_rgbled.c
View file

@ -41,8 +41,6 @@
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_PWM_MULTICHAN
/* PWM0 channels 0, 1 and 2 used */
# if !defined(CONFIG_NRF53_PWM0_CH0) || !defined(CONFIG_NRF53_PWM0_CH1) || \
@ -50,16 +48,6 @@
# error Invalid configuration for RGBLED driver
# endif
#else
/* PWM0 channel 0, PWM1 channel 0 and PWM2 channel 0 used */
# if !defined(CONFIG_NRF53_PWM0_CH0) || !defined(CONFIG_NRF53_PWM1_CH0) || \
!defined(CONFIG_NRF53_PWM2_CH0)
# error Invalid configuration for RGBLED driver
# endif
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -96,10 +84,6 @@ int nrf53_rgbled_initialize(void)
/* Define frequency and duty cycle */
#ifndef CONFIG_PWM_MULTICHAN
info.frequency = 100;
info.duty = 0;
#else
ledg = ledr;
ledb = ledr;
@ -107,50 +91,15 @@ int nrf53_rgbled_initialize(void)
info.channels[0].duty = 0;
info.channels[1].duty = 0;
info.channels[2].duty = 0;
#endif
/* Initialize LED R */
ledr->ops->setup(ledr);
ledr->ops->start(ledr, &info);
#ifndef CONFIG_PWM_MULTICHAN
/* Call nrf53_pwminitialize() to get an instance of the PWM interface */
ledg = nrf53_pwminitialize(1);
if (!ledg)
{
lederr("ERROR: Failed to get the NRF53 PWM lower half to LEDG\n");
return -ENODEV;
}
/* Initialize LED G */
ledg->ops->setup(ledg);
ledg->ops->start(ledg, &info);
/* Call nrf53_pwminitialize() to get an instance of the PWM interface */
ledb = nrf53_pwminitialize(2);
if (!ledb)
{
lederr("ERROR: Failed to get the NRF53 PWM lower half to LEDB\n");
return -ENODEV;
}
/* Initialize LED B */
ledb->ops->setup(ledb);
ledb->ops->start(ledb, &info);
#endif
/* Register the RGB LED diver at "/dev/rgbled0" */
#ifdef CONFIG_PWM_MULTICHAN
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, 1, 2, 3);
#else
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb);
#endif
if (ret < 0)
{
lederr("ERROR: rgbled_register failed: %d\n", ret);

32
boards/arm/rp2040/common/Kconfig
View file

@ -271,7 +271,7 @@ config RP2040_PWM0A_GPIO
either 0 or 16, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM0B_GPIO
int "GPIO pin for PWM0 channel 2 (1, 17 or -1:no assign)"
@ -282,7 +282,7 @@ config RP2040_PWM0B_GPIO
either 1 or 17, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM0
@ -299,7 +299,7 @@ config RP2040_PWM1A_GPIO
either 2 or 18, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM1B_GPIO
int "GPIO pin for PWM1 channel 2 (3, 19 or -1:no assign)"
@ -310,7 +310,7 @@ config RP2040_PWM1B_GPIO
either 3 or 19, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM1
@ -327,7 +327,7 @@ config RP2040_PWM2A_GPIO
either 4 or 20, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM2B_GPIO
int "GPIO pin for PWM2 channel 2 (5, 21 or -1:no assign)"
@ -338,7 +338,7 @@ config RP2040_PWM2B_GPIO
either 5 or 21, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM2
@ -355,7 +355,7 @@ config RP2040_PWM3A_GPIO
either 6 or 22, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM3B_GPIO
int "GPIO pin for PWM3 channel 2 (7, 23 or -1:no assign)"
@ -366,7 +366,7 @@ config RP2040_PWM3B_GPIO
either 7 or 23, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM3
@ -383,7 +383,7 @@ config RP2040_PWM4A_GPIO
either 8 or 24, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM4B_GPIO
int "GPIO pin for PWM4 channel 2 (9, 25 or -1:no assign)"
@ -394,7 +394,7 @@ config RP2040_PWM4B_GPIO
either 9 or 25, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM4
@ -411,7 +411,7 @@ config RP2040_PWM5A_GPIO
either 10 or 26, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM5B_GPIO
int "GPIO pin for PWM5 channel 2 (11, 27 or -1:no assign)"
@ -422,7 +422,7 @@ config RP2040_PWM5B_GPIO
either 11 or 27, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM5
@ -439,7 +439,7 @@ config RP2040_PWM6A_GPIO
either 12 or 28, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM6B_GPIO
int "GPIO pin for PWM6 channel 2 (13, 29 or -1:no assign)"
@ -450,7 +450,7 @@ config RP2040_PWM6B_GPIO
either 13 or 29, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM6
@ -467,7 +467,7 @@ config RP2040_PWM7A_GPIO
either 14, any other value disables the output.
Refer to board documentation to see if pin 14 is available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP2040_PWM7B_GPIO
int "GPIO pin for PWM7 channel 2 (15 or -1:no assign)"
@ -478,7 +478,7 @@ config RP2040_PWM7B_GPIO
either 15, any other value disables the output.
Refer to board documentation to see if pin 15 is available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP2040_PWM7

32
boards/arm/rp23xx/common/Kconfig
View file

@ -272,7 +272,7 @@ config RP23XX_PWM0A_GPIO
either 0 or 16, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM0B_GPIO
int "GPIO pin for PWM0 channel 2 (1, 17 or -1:no assign)"
@ -283,7 +283,7 @@ config RP23XX_PWM0B_GPIO
either 1 or 17, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM0
@ -300,7 +300,7 @@ config RP23XX_PWM1A_GPIO
either 2 or 18, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM1B_GPIO
int "GPIO pin for PWM1 channel 2 (3, 19 or -1:no assign)"
@ -311,7 +311,7 @@ config RP23XX_PWM1B_GPIO
either 3 or 19, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM1
@ -328,7 +328,7 @@ config RP23XX_PWM2A_GPIO
either 4 or 20, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM2B_GPIO
int "GPIO pin for PWM2 channel 2 (5, 21 or -1:no assign)"
@ -339,7 +339,7 @@ config RP23XX_PWM2B_GPIO
either 5 or 21, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM2
@ -356,7 +356,7 @@ config RP23XX_PWM3A_GPIO
either 6 or 22, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM3B_GPIO
int "GPIO pin for PWM3 channel 2 (7, 23 or -1:no assign)"
@ -367,7 +367,7 @@ config RP23XX_PWM3B_GPIO
either 7 or 23, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM3
@ -384,7 +384,7 @@ config RP23XX_PWM4A_GPIO
either 8 or 24, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM4B_GPIO
int "GPIO pin for PWM4 channel 2 (9, 25 or -1:no assign)"
@ -395,7 +395,7 @@ config RP23XX_PWM4B_GPIO
either 9 or 25, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM4
@ -412,7 +412,7 @@ config RP23XX_PWM5A_GPIO
either 10 or 26, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM5B_GPIO
int "GPIO pin for PWM5 channel 2 (11, 27 or -1:no assign)"
@ -423,7 +423,7 @@ config RP23XX_PWM5B_GPIO
either 11 or 27, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM5
@ -440,7 +440,7 @@ config RP23XX_PWM6A_GPIO
either 12 or 28, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM6B_GPIO
int "GPIO pin for PWM6 channel 2 (13, 29 or -1:no assign)"
@ -451,7 +451,7 @@ config RP23XX_PWM6B_GPIO
either 13 or 29, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM6
@ -468,7 +468,7 @@ config RP23XX_PWM7A_GPIO
either 14, any other value disables the output.
Refer to board documentation to see if pin 14 is available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_PWM7B_GPIO
int "GPIO pin for PWM7 channel 2 (15 or -1:no assign)"
@ -479,7 +479,7 @@ config RP23XX_PWM7B_GPIO
either 15, any other value disables the output.
Refer to board documentation to see if pin 15 is available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_PWM7

1
boards/arm/samv7/same70-xplained/configs/pwm/defconfig
View file

@ -56,7 +56,6 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=393216
CONFIG_RAM_START=0x20400000

1
boards/arm/samv7/same70-xplained/configs/pysim/defconfig
View file

@ -101,7 +101,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PTHREAD_STACK_DEFAULT=2048
CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=393216
CONFIG_RAM_START=0x20400000

6
boards/arm/stm32/common/src/stm32_tone.c
View file

@ -44,6 +44,10 @@
* Pre-processor Definitions
****************************************************************************/
#ifndef BOARD_TONE_PWM_CHANNEL
# define BOARD_TONE_PWM_CHANNEL 1
#endif
/****************************************************************************
* Private Types
****************************************************************************/
@ -117,7 +121,7 @@ int board_tone_initialize(int devno)
/* Register the Audio Tone driver at "/dev/tone0" */
snprintf(devpath, sizeof(devpath), "/dev/tone%d", devno);
ret = tone_register(devpath, tone, oneshot);
ret = tone_register(devpath, tone, BOARD_TONE_PWM_CHANNEL, oneshot);
if (ret < 0)
{
auderr("ERROR: tone_register failed: %d\n", ret);

4
boards/arm/stm32/common/src/stm32_xen1210.c
View file

@ -225,8 +225,8 @@ static int xen1210_pwm_setup(void)
/* Define frequency and duty cycle: 2MHz @ 50% */
info.frequency = 2000000; /* 2MHz */
info.duty = 32768; /* This value means 50% */
info.frequency = 2000000; /* 2MHz */
info.channels[0].duty = 32768; /* This value means 50% */
/* Initialize PWM */

1
boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig
View file

@ -24,7 +24,6 @@ CONFIG_MM_REGIONS=2
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=2
CONFIG_RAM_SIZE=65536
CONFIG_RAM_START=0x20000000

1
boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig
View file

@ -25,7 +25,6 @@ CONFIG_LINE_MAX=80
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=1024
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=4
CONFIG_RAM_SIZE=22528
CONFIG_RAM_START=0x20000000

1
boards/arm/stm32/omnibusf4/configs/nsh/defconfig
View file

@ -64,7 +64,6 @@ CONFIG_NSH_READLINE=y
CONFIG_PIPES=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000

1
boards/arm/stm32/photon/configs/rgbled/defconfig
View file

@ -37,7 +37,6 @@ CONFIG_PHOTON_IWDG=y
CONFIG_PHOTON_WDG_THREAD=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=4
CONFIG_RAMLOG=y
CONFIG_RAMLOG_BUFSIZE=8192

8
boards/arm/stm32/photon/src/stm32_rgbled.c
View file

@ -57,10 +57,6 @@
# undef HAVE_RGBLED
#endif
#ifndef CONFIG_PWM_MULTICHAN
# undef HAVE_RGBLED
#endif
#ifndef CONFIG_STM32_TIM2_PWM
# undef HAVE_RGBLED
#endif
@ -139,13 +135,9 @@ int stm32_rgbled_setup(void)
/* Register the RGB LED diver at "/dev/rgbled0" */
#ifdef CONFIG_PWM_MULTICHAN
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb,
RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL,
RGBLED_BPWMCHANNEL);
#else
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb);
#endif
if (ret < 0)
{
lederr("ERROR: rgbled_register failed: %d\n", ret);

1
boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig
View file

@ -32,6 +32,7 @@ CONFIG_LINE_MAX=80
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=1024
CONFIG_PWM=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=20480
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y

1
boards/arm/stm32/stm32f103-minimum/include/board.h
View file

@ -186,6 +186,7 @@
/* Tone Driver **************************************************************/
#define BOARD_TONE_PWM_TIM 2 /* PWM timer for tone generation */
#define BOARD_TONE_PWM_CHANNEL 2 /* PWM channel for tone generation */
#define BOARD_TONE_ONESHOT_TIM 3 /* Oneshot timer for note timings */
#define BOARD_TONE_ONESHOT_TIM_RES 10 /* Oneshot timer resolution (us) */

6
boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c
View file

@ -126,7 +126,7 @@ int stm32_rgbled_setup(void)
/* Define frequency and duty cycle */
info.frequency = 100;
info.duty = 0;
info.channels[0].duty = 0;
/* Initialize LED R */
@ -163,7 +163,9 @@ int stm32_rgbled_setup(void)
/* Register the RGB LED diver at "/dev/rgbled0" */
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb);
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb,
RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL,
RGBLED_BPWMCHANNEL);
if (ret < 0)
{
lederr("ERROR: rgbled_register failed: %d\n", ret);

1
boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig
View file

@ -32,6 +32,7 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y

6
boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c
View file

@ -126,7 +126,7 @@ int stm32_rgbled_setup(void)
/* Define frequency and duty cycle */
info.frequency = 100;
info.duty = 0;
info.channels[0].duty = 0;
/* Initialize LED R */
@ -163,7 +163,9 @@ int stm32_rgbled_setup(void)
/* Register the RGB LED diver at "/dev/rgbled0" */
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb);
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb,
RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL,
RGBLED_BPWMCHANNEL);
if (ret < 0)
{
lederr("ERROR: rgbled_register failed: %d\n", ret);

1
boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig
View file

@ -31,6 +31,7 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y

6
boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c
View file

@ -114,7 +114,7 @@ int stm32_rgbled_setup(void)
/* Define frequency and duty cycle */
info.frequency = 100;
info.duty = 0;
info.channels[0].duty = 0;
/* Initialize LED R */
@ -151,7 +151,9 @@ int stm32_rgbled_setup(void)
/* Register the RGB LED diver at "/dev/rgbled0" */
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb);
ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb,
1, CONFIG_STM32_TIM2_CHANNEL,
CONFIG_STM32_TIM3_CHANNEL);
if (ret < 0)
{
lederr("ERROR: rgbled_register failed: %d\n", ret);

1
boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig
View file

@ -50,7 +50,6 @@ CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536
CONFIG_PTHREAD_MUTEX_UNSAFE=y
CONFIG_PTHREAD_STACK_DEFAULT=1536
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_RAM_SIZE=20480
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y

1
boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig
View file

@ -75,7 +75,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PTHREAD_STACK_DEFAULT=2048
CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=2
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

1
boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig
View file

@ -74,7 +74,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PTHREAD_STACK_DEFAULT=2048
CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=2
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

1
boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h
View file

@ -104,6 +104,7 @@
/* PWM */
#define BUZZER_PWMTIMER 4
#define BUZZER_PWMCHANNEL 2
/* OneShot Timer */

2
boards/arm/stm32h7/linum-stm32h753bi/src/stm32_tone.c
View file

@ -155,7 +155,7 @@ int board_tone_initialize(int devno)
/* Register the Audio Tone driver at "/dev/tone0" */
snprintf(devpath, 12, "/dev/tone%d", devno);
ret = tone_register(devpath, tone, oneshot);
ret = tone_register(devpath, tone, BUZZER_PWMCHANNEL, oneshot);
if (ret < 0)
{
auderr("ERROR: tone_register failed: %d\n", ret);

1
boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig
View file

@ -35,7 +35,6 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=4
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

1
boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig
View file

@ -72,7 +72,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PTHREAD_STACK_DEFAULT=2048
CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000
CONFIG_RAW_BINARY=y

1
boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig
View file

@ -72,7 +72,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PTHREAD_STACK_DEFAULT=2048
CONFIG_PTHREAD_STACK_MIN=1024
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000
CONFIG_RAW_BINARY=y

1
boards/risc-v/bl602/bl602evb/configs/timer/defconfig
View file

@ -59,7 +59,6 @@ CONFIG_NSH_STRERROR=y
CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192
CONFIG_PTHREAD_STACK_DEFAULT=8192
CONFIG_PWM=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=2
CONFIG_RAM_SIZE=134217728
CONFIG_RAM_START=0xc0800000

32
boards/risc-v/rp23xx-rv/common/Kconfig
View file

@ -272,7 +272,7 @@ config RP23XX_RV_PWM0A_GPIO
either 0 or 16, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM0B_GPIO
int "GPIO pin for PWM0 channel 2 (1, 17 or -1:no assign)"
@ -283,7 +283,7 @@ config RP23XX_RV_PWM0B_GPIO
either 1 or 17, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM0
@ -300,7 +300,7 @@ config RP23XX_RV_PWM1A_GPIO
either 2 or 18, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM1B_GPIO
int "GPIO pin for PWM1 channel 2 (3, 19 or -1:no assign)"
@ -311,7 +311,7 @@ config RP23XX_RV_PWM1B_GPIO
either 3 or 19, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM1
@ -328,7 +328,7 @@ config RP23XX_RV_PWM2A_GPIO
either 4 or 20, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM2B_GPIO
int "GPIO pin for PWM2 channel 2 (5, 21 or -1:no assign)"
@ -339,7 +339,7 @@ config RP23XX_RV_PWM2B_GPIO
either 5 or 21, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM2
@ -356,7 +356,7 @@ config RP23XX_RV_PWM3A_GPIO
either 6 or 22, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM3B_GPIO
int "GPIO pin for PWM3 channel 2 (7, 23 or -1:no assign)"
@ -367,7 +367,7 @@ config RP23XX_RV_PWM3B_GPIO
either 7 or 23, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM3
@ -384,7 +384,7 @@ config RP23XX_RV_PWM4A_GPIO
either 8 or 24, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM4B_GPIO
int "GPIO pin for PWM4 channel 2 (9, 25 or -1:no assign)"
@ -395,7 +395,7 @@ config RP23XX_RV_PWM4B_GPIO
either 9 or 25, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM4
@ -412,7 +412,7 @@ config RP23XX_RV_PWM5A_GPIO
either 10 or 26, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM5B_GPIO
int "GPIO pin for PWM5 channel 2 (11, 27 or -1:no assign)"
@ -423,7 +423,7 @@ config RP23XX_RV_PWM5B_GPIO
either 11 or 27, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM5
@ -440,7 +440,7 @@ config RP23XX_RV_PWM6A_GPIO
either 12 or 28, any other value disables the output.
Refer to board documentation to see which pins are available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM6B_GPIO
int "GPIO pin for PWM6 channel 2 (13, 29 or -1:no assign)"
@ -451,7 +451,7 @@ config RP23XX_RV_PWM6B_GPIO
either 13 or 29, any other value disables the output.
Refer to board documentation to see which pins are available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM6
@ -468,7 +468,7 @@ config RP23XX_RV_PWM7A_GPIO
either 14, any other value disables the output.
Refer to board documentation to see if pin 14 is available.
if PWM_MULTICHAN && PWM_NCHANNELS > 1
if PWM_NCHANNELS > 1
config RP23XX_RV_PWM7B_GPIO
int "GPIO pin for PWM7 channel 2 (15 or -1:no assign)"
@ -479,7 +479,7 @@ config RP23XX_RV_PWM7B_GPIO
either 15, any other value disables the output.
Refer to board documentation to see if pin 15 is available.
endif # PWM_MULTICHAN && PWM_NCHANNELS > 1
endif # PWM_NCHANNELS > 1
endif # RP23XX_RV_PWM7

2
boards/xtensa/esp32/common/src/esp32_rgbled.c
View file

@ -51,7 +51,7 @@
defined(CONFIG_ESP32_LEDC) && \
defined(CONFIG_ESP32_LEDC_TIM0) && \
(CONFIG_ESP32_LEDC_TIM0_CHANNELS >= 3) && \
defined(CONFIG_PWM_MULTICHAN) && (CONFIG_PWM_NCHANNELS >= 3)
(CONFIG_PWM_NCHANNELS >= 3)
/****************************************************************************
* Public Functions

1
boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig
View file

@ -86,7 +86,6 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_IRQ_MSGS=512
CONFIG_PREALLOC_MQ_MSGS=512
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000

1
boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig
View file

@ -106,7 +106,6 @@ CONFIG_NSH_MMCSDSPIPORTNO=2
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000

1
boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig
View file

@ -83,7 +83,6 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_MMCSDSPIPORTNO=2
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000

1
boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig
View file

@ -110,7 +110,6 @@ CONFIG_NSH_READLINE=y
CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048
CONFIG_PREALLOC_TIMERS=4
CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=3
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000

1
boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig
View file

@ -44,7 +44,6 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PWM_MULTICHAN=y
CONFIG_PWM_NCHANNELS=2
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000

2
boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c
View file

@ -106,7 +106,7 @@ int board_lcd_initialize(void)
/* Turn on LCD backlight (10% brightness) */
pwm.frequency = SZPI_LCD_PWM_FREQ;
pwm.duty = SZPI_LCD_PWM_DUTY;
pwm.channels[0].duty = SZPI_LCD_PWM_DUTY;
ret = file_open(&g_pwm_file, SZPI_LCD_PWM_PATH, O_RDONLY);
if (ret < 0)

14
drivers/audio/tone.c
View file

@ -83,9 +83,7 @@ struct tone_upperhalf_s
{
uint8_t crefs; /* The number of times the device has been
* opened */
#ifdef CONFIG_PWM_MULTICHAN
uint8_t channel; /* Output channel that drives the tone. */
#endif
volatile bool started; /* True: pulsed output is being generated */
mutex_t lock; /* Supports mutual exclusion */
struct pwm_info_s tone; /* Pulsed output for Audio Tone */
@ -290,12 +288,8 @@ static void start_note(FAR struct tone_upperhalf_s *upper, uint8_t note)
FAR struct pwm_lowerhalf_s *tone = upper->devtone;
upper->tone.frequency = g_notes_freq[note - 1];
#ifdef CONFIG_PWM_MULTICHAN
upper->tone.channels[0].channel = upper->channel;
upper->tone.channels[0].duty = b16HALF;
#else
upper->tone.duty = b16HALF;
#endif
/* REVISIT: Should check the return value */
@ -310,12 +304,8 @@ static void stop_note(FAR struct tone_upperhalf_s *upper)
{
FAR struct pwm_lowerhalf_s *tone = upper->devtone;
#ifdef CONFIG_PWM_MULTICHAN
upper->tone.channels[0].channel = upper->channel;
upper->tone.channels[0].duty = 0;
#else
upper->tone.duty = 0;
#endif
/* REVISIT: Should check the return value */
@ -929,9 +919,7 @@ static ssize_t tone_write(FAR struct file *filep, FAR const char *buffer,
****************************************************************************/
int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone,
#ifdef CONFIG_PWM_MULTICHAN
int channel,
#endif
FAR struct oneshot_lowerhalf_s *oneshot)
{
FAR struct tone_upperhalf_s *upper;
@ -954,9 +942,7 @@ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone,
nxmutex_init(&upper->lock);
upper->devtone = tone;
upper->oneshot = oneshot;
#ifdef CONFIG_PWM_MULTICHAN
upper->channel = (uint8_t)channel;
#endif
upper->oneshot->callback = oneshot_callback;
upper->oneshot->arg = upper;

1
drivers/leds/Kconfig
View file

@ -74,6 +74,7 @@ config LEDS_MAX7219
config RGBLED
bool "RGB LED Driver Support"
default n
depends on PWM_NCHANNELS >= 3
---help---
This selection enables building of the "upper-half" RGB LED driver.
See include/nuttx/rgbled.h for further PWM driver information.

24
drivers/leds/rgbled.c
View file

@ -62,11 +62,9 @@ struct rgbled_upperhalf_s
FAR struct pwm_lowerhalf_s *devledr;
FAR struct pwm_lowerhalf_s *devledg;
FAR struct pwm_lowerhalf_s *devledb;
#ifdef CONFIG_PWM_MULTICHAN
int chanr; /* Red PWM channel */
int chang; /* Green PWM channel */
int chanb; /* Blue PWM channel */
#endif
};
/****************************************************************************
@ -280,9 +278,7 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer,
unsigned int green;
unsigned int blue;
char color[3];
#ifdef CONFIG_PWM_MULTICHAN
int i;
#endif
/* We need to receive a string #RRGGBB = 7 bytes */
@ -359,7 +355,6 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer,
blue ^= 0xffff;
#endif
#ifdef CONFIG_PWM_MULTICHAN
memset(&pwm, 0, sizeof(struct pwm_info_s));
pwm.frequency = CONFIG_RGBLED_PWM_FREQ;
@ -433,18 +428,6 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer,
ledb->ops->start(ledb, &pwm);
}
#else
pwm.frequency = CONFIG_RGBLED_PWM_FREQ;
pwm.duty = red;
ledr->ops->start(ledr, &pwm);
pwm.duty = green;
ledg->ops->start(ledg, &pwm);
pwm.duty = blue;
ledb->ops->start(ledb, &pwm);
#endif
return buflen;
}
@ -471,8 +454,7 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer,
* drivers for the red, green, and blue LEDs, respectively. These
* instances will be bound to the RGB LED driver and must persists as
* long as that driver persists.
* chanr, chang, chanb -Red/Green/Blue PWM channels (only if
* CONFIG_PWM_MULTICHAN is defined)
* chanr, chang, chanb -Red/Green/Blue PWM channels
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@ -482,9 +464,7 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer,
int rgbled_register(FAR const char *path, FAR struct pwm_lowerhalf_s *ledr,
FAR struct pwm_lowerhalf_s *ledg,
FAR struct pwm_lowerhalf_s *ledb
#ifdef CONFIG_PWM_MULTICHAN
, int chanr, int chang, int chanb
#endif
)
{
FAR struct rgbled_upperhalf_s *upper;
@ -509,11 +489,9 @@ int rgbled_register(FAR const char *path, FAR struct pwm_lowerhalf_s *ledr,
upper->devledg = ledg;
upper->devledb = ledb;
#ifdef CONFIG_PWM_MULTICHAN
upper->chanr = chanr;
upper->chang = chang;
upper->chanb = chanb;
#endif
/* Register the PWM device */

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