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At system startup, the NVIC was configured for proper default priority only for the first three IPR registers, even though the loop was executed 13 times - due to a gotcha on what the `NVIC_IRQ_PRIORITY(i)` macro returns. IRQs 12-51 stayed at the reset priority of 0 - highest in the system; so any peripherals issuing those interrupts will shoot through critical sections that rely on BASEPRI = NVIC_SYSH_PRIORITY_DEFAULT (0x80). This can corrupt the TCB ready-to-run list and semaphore wait queues; this is hard to reproduce (e.g. in ostest) because it requires a peripheral ISR to land inside a critical section, but the failure modes range from hangs to wild pointer crashes once it does. In my case I had SPI and I2C peripherals that were issuing IRQs and were preempting scheduler and semaphore list operations, causing corruption. Step the loop by four and bound it with RP23XX_IRQ_NEXTINT so every IPR covering IRQs 0..51 is written once with DEFPRIORITY32. Signed-off-by: Daniel Fanache <dan@rts.ro> |
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