Aksal/nuttx
3
1
Fork 1
mirror of https://github.com/apache/nuttx.git synced 2026-10-07 22:35:22 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

Documentation/stm32h5: document the ICACHE and the MPU.

Browse source 
Add an ICACHE section to the STM32H5 platform page.  With
CONFIG_STM32_ICACHE the OTP, read-only and EDATA flash areas are mapped
non-cacheable with an MPU region, so they can be read like any other
memory.

The MPU is not applied in the HardFault and NMI handlers (HFNMIENA=0),
so these areas must not be read from NMI or HardFault context: with the
ICACHE enabled such a read raises a bus fault.

Assisted-by: Claude:claude-sonnet-5-5
Signed-off-by: Ricardo Maurizio Paul <ricardopaul@geotab.com>
This commit is contained in:
Ricardo Maurizio Paul 2026-10-06 12:07:59 +02:00 • committed by Alan C. Assis
parent aee40e2348
commit 36149b775e
1 changed files with 11 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

11
Documentation/platforms/arm/stm32h5/index.rst
View file

@ -85,6 +85,17 @@ OTP Yes
========== ======= =====
ICACHE
------
With ``CONFIG_STM32_ICACHE`` the OTP, read-only (UID, flash size, package) and
EDATA flash areas (0x08fff000-0x09017fff) are mapped non-cacheable with an MPU
region, so they can be read like any other memory.
The MPU is not applied in the HardFault and NMI handlers (``HFNMIENA=0``), so
these areas must not be read from NMI or HardFault context: with the ICACHE
enabled such a read raises a bus fault.
USB FS Host
-----------