diff --git a/Documentation/platforms/arm/stm32h5/index.rst b/Documentation/platforms/arm/stm32h5/index.rst
index 4432d1a0bcf..c60d0d8969b 100644
--- a/Documentation/platforms/arm/stm32h5/index.rst
+++ b/Documentation/platforms/arm/stm32h5/index.rst
@@ -85,6 +85,17 @@ OTP         Yes
 
 ==========  =======  =====
 
+ICACHE
+------
+
+With ``CONFIG_STM32_ICACHE`` the OTP, read-only (UID, flash size, package) and
+EDATA flash areas (0x08fff000-0x09017fff) are mapped non-cacheable with an MPU
+region, so they can be read like any other memory.
+
+The MPU is not applied in the HardFault and NMI handlers (``HFNMIENA=0``), so
+these areas must not be read from NMI or HardFault context: with the ICACHE
+enabled such a read raises a bus fault.
+
 USB FS Host
 -----------