From 36149b775ef8430ff892d16a00cdc74af841e2e7 Mon Sep 17 00:00:00 2001 From: Ricardo Maurizio Paul Date: Tue, 6 Oct 2026 12:07:59 +0200 Subject: [PATCH] Documentation/stm32h5: document the ICACHE and the MPU. Add an ICACHE section to the STM32H5 platform page. With CONFIG_STM32_ICACHE the OTP, read-only and EDATA flash areas are mapped non-cacheable with an MPU region, so they can be read like any other memory. The MPU is not applied in the HardFault and NMI handlers (HFNMIENA=0), so these areas must not be read from NMI or HardFault context: with the ICACHE enabled such a read raises a bus fault. Assisted-by: Claude:claude-sonnet-5-5 Signed-off-by: Ricardo Maurizio Paul --- Documentation/platforms/arm/stm32h5/index.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/platforms/arm/stm32h5/index.rst b/Documentation/platforms/arm/stm32h5/index.rst index 4432d1a0bcf..c60d0d8969b 100644 --- a/Documentation/platforms/arm/stm32h5/index.rst +++ b/Documentation/platforms/arm/stm32h5/index.rst @@ -85,6 +85,17 @@ OTP Yes ========== ======= ===== +ICACHE +------ + +With ``CONFIG_STM32_ICACHE`` the OTP, read-only (UID, flash size, package) and +EDATA flash areas (0x08fff000-0x09017fff) are mapped non-cacheable with an MPU +region, so they can be read like any other memory. + +The MPU is not applied in the HardFault and NMI handlers (``HFNMIENA=0``), so +these areas must not be read from NMI or HardFault context: with the ICACHE +enabled such a read raises a bus fault. + USB FS Host -----------