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The OTP, read-only (UID, flash size, package) and high-cycle data (EDATA) flash areas only accept 16/32-bit accesses and return a bus error otherwise (RM0481 Table 77). The manual requires the MPU to disable local cacheability for them (RM0481 7.3.2); with the ICACHE enabled and no such region, reading them raises a precise bus error. Until now this was worked around piecemeal: the driver disabled the ICACHE around stm32_get_uniqueid() and the OTP and EDATA word reads, and nucleo-h563zi mapped the 4 KB OTP/RO area non-cacheable in its board code. Other reads, for example stm32_otp_read() or an application reading the OTP on another board, still raised a precise bus error when the ICACHE was enabled. Map 0x08fff000-0x09017fff, which covers the three contiguous areas, as Normal non-cacheable and execute-never with a single MPU region before the ICACHE is enabled. STM32_ICACHE now selects ARM_MPU so that stm32_mpuinitialize() has reset and enabled the MPU by then. Remove the nucleo-h563zi OTP region in the same commit: the Armv8-M MPU faults on an address that matches more than one region, so keeping both would make OTP and UID reads fault on that board. Assisted-by: Claude:claude-sonnet-5-5 Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Ricardo Maurizio Paul <ricardopaul@geotab.com> |
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| common | ||
| nucleo-h503rb | ||
| nucleo-h533re | ||
| nucleo-h563zi | ||
| stm32h573i-dk | ||