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The SSE-200 subsystem the AN521 image implements lists the UART interrupts receive first: UART0 RX is external interrupt 32 and UART0 TX is 33, which in NuttX numbering are 48 and 49. The configuration had those two the wrong way round, so the TX interrupt was dispatched to uart_cmsdk_rx_interrupt. That handler clears only UART_INTSTATUS_RX, so the asserted TX status bit survived the acknowledgement and the interrupt re-fired immediately. The board live-locked in the interrupt handler as soon as the console emitted its first character: the NSH banner appeared, and nothing ran afterwards, console input included. Note that the overflow interrupt already sits at 63, external 47, which is where the SSE-200 map puts it only if the pair below it is receive first -- the two corrected values are the ones consistent with it. mps2-an500 already follows the same order with RX at 16 and TX at 17. Assisted-by: Claude Code:claude-opus-5 Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| dummy | ||
| hc/m9s12 | ||
| mips | ||
| misoc/lm32/misoc | ||
| or1k/mor1kx/or1k | ||
| renesas | ||
| risc-v | ||
| sim/sim/sim | ||
| sparc | ||
| tricore | ||
| x86/qemu/qemu-i486 | ||
| x86_64/qemu/qemu-intel64 | ||
| xtensa | ||
| z16/z16f/z16f2800100zcog | ||
| z80 | ||
| .gitignore | ||
| Board.mk | ||
| boardctl.c | ||
| CMakeLists.txt | ||
| dummy.c | ||
| Kconfig | ||
| Makefile | ||