If CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE is defined, the coremmc driver
uses SD card's dat0 line to detect whether the sd card is still busy.
This requires that the FPGA design using coremmc block wires dat0 line
to some fabric irq; and configures CONFIG_MPFS_COREMMC_WRCOMPLETE_IRQNUM
to point to that. Default for the irq number is 4. (MSS_INT_F2M_4)
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This adds minimal support for NXP MCX-N236 CPU. Peripherals supported are:
- GPIO
- PINMUX
- CLOCK
- LPUART
An example board, FRDM-MCXN236 is also added, with a basic profile that
boots into nsh.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
From Polarfire SoC TRM:
6.5.8 Interrupt Completion
To signal the completion of executing an interrupt handler, the processor core writes the received interrupt ID to the
Claim/Complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that
target. If the completion ID does not match an interrupt source that is currently enabled for the target, the completion
is ignored.
The last paragraph clearly states that IRQ completion does not work for
sources that have been disabled -> must ACK the completion before disable.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
This commit allows placing .bss data into the external PSRAM.
Previously, the PSRAM was fully allocated to the heap memory only
and now part of it can be used to allocate .bss data freeing the
internal memory.
on ESP32, cpuint was allocated when register wdt handler, but not
deallocated when unregister, which cause debug assert when checking
`DEBUGASSERT((*freeints & bitmask) == 0)`, so set cpuint to initial value
after deallocate.
The same issue on ESP32s3 has been fixed by PR#15433
Update the wireless symbols from ESP32S3_* to ESPRESSIF_* for using common layer.
Remove ESP32S3 specific WiFi files and edit build system to use common layer.
Instead of enabling an interrupt on the calling hart, enable it on every
hart. This should balance the interrupt load some, especially in cases
where the interrupt source is enabled only once (which will almost
certainly happen on CPU 0 only).
Signed-off-by: Ville Juven <ville.juven@unikie.com>
When the l1entry first add to shm, mssing l1entry add.
shm mmu flags should use udata flags.
l1entry record in shm[] and should not use ~SECTION_MASK
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
chip/sam_1wire.c:921:7: warning: implicit declaration of function 'sam_usart0_enableclk' [-Wimplicit-function-declaration]
921 | sam_usart0_enableclk();
The same warning applied for other uart/usart peripherals configured
as 1 wire.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds support to TIOCGICOUNT for STM32, this way a
userspace application can collect information about UART errors.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Fixes bug where stm32_phyinit will succeed even when no PHY is connected. This is because there is no check that a PHY is actually communicating and returning data.
Update include/nuttx/net/mii.h
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
Due to interrupt latencies the i2c transfer done interrupt can get
deferred by a few hunder microseconds. This makes the i2c transfer timeout
way too early, even though the i2c IP block is already done.
Fix this by adding a significant amount of margin (1ms) to the timeout
value.
This removes several error conditions that can be present after a failed
i2c transaction. The most important of them is the priv->sem_isr semaphore
which can be signaled due to a race condition.
This also ensures the i2c device itself is in idle state before futzing
around with it.
Also, add a comment about the SI-flag in the I2C CTRL register; it has
a hidden dual meaning. Not only does it clear a pending interrupt, it
also moves the I2C IP state machine forward. This requires extra logic
in the driver to cope.
