Commit graph

1973 commits

Author SHA1 Message Date
Filipe Cavalcanti
680766d304 arch/xtensa: update SPI Flash driver for ESP32-S2|S3
Updates the SPI Flash driver used for user storage MTD.
Moves ESP32 and ESP32S3 to use common driver.
Updates KConfig options to keep backwards compatibility.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-10-29 09:44:55 -04:00
Vlad Pruteanu
8a10e35c0b arch/xtensa/esp32: Fix support for hardware accelerated AES
Curently, the driver code for HW accelerated AES is not usable
since it's not registered within esp32_crypto. This commit fixes
it as well as a few bugs.

Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
2025-10-24 11:20:04 -03:00
Eren Terzioglu
a590599c7e arch/xtensa/esp32[-s3]: Add ULP RISCV coprocessor wakeup
Add ULP RISCV coprocessor wakeup support for esp32s3

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-24 11:16:11 +08:00
Eren Terzioglu
734068890a arch/xtensa/esp32[-|-s3]: Fix exception issue when pm active
Fix exception issue when PM and DEBUG_ASSERTIONS enabled for esp32 and esp32s3.
This error happens due to PM system workflow, when system gets into sleep-modes with
removing PM_NORMAL count, system is raising an exception for not having
enough number of PM_NORMAL state count if DEBUG_ASSERTIONS enabled.

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-23 09:38:26 -04:00
Eren Terzioglu
24eeff91c0 arch/xtensa/esp32[-s2|-s3]: Add multiple ULP RISC-V bin support
Add multiple ULP RISC-V bin support for esp32s2 and esp32s3

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-21 06:32:32 -03:00
Thiago Finelon
42d5f10c0d arch/xtensa/esp32s3: expose UART RX FIFO controls
Adds Kconfig knobs for the ESP32-S3 RX FIFO full threshold and timeout and wires them into the UART driver.
Clears RX FIFO overflow interrupts by resetting the hardware FIFO so reception resumes cleanly.

Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
2025-10-17 17:40:32 +08:00
chao an
87f134cfaa sched/sleep: replace all Signal-based sleep implement to Scheduled sleep
Nuttx currently has 2 types of sleep interfaces:

1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.

2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.

3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.

Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.

(This PR also aims to make signals optional, further reducing the code size of Nuttx.)

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-10-17 14:05:02 +08:00
Filipe Cavalcanti
7297ecc02e arch/xtensa: add non-iram interrupt support for ESP32-S2
Adds support for enabling and disabling non-iram interrupts on ESP32-S2.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-10-16 17:06:05 -04:00
Filipe Cavalcanti
df6e5384fe arch/xtensa: update MCUBoot and virtual E-Fuse offset
Updates MCUBoot version and default address for virtual E-Fuse, depending
if MCUBoot is enabled.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-10-14 17:44:15 +08:00
guoshengyuan1
79711737bc arch/init: call up_color_intstack before up_irq_enable
Make sure interrupt stack is colored before IRQ is enabled.

Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.

Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
2025-10-14 17:42:01 +08:00
Eren Terzioglu
7e2a06959a arch/xtensa/espressif: Fix efuse build warning for esp32
Fix build warning while building efuse for esp32

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-07 15:18:36 +02:00
Thiago Finelon
7fe0fbd9b8 uart: fix FSM check to avoid PM deadlocks
Incorrect FSM status checks in the suspend path could cause
deadlocks when power management was enabled. This patch fixes
the condition to allow proper UART suspend/resume handling.

Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
2025-10-06 09:03:03 -03:00
Eren Terzioglu
09c298ed16 arch/xtensa/esp32[-s2|-s3]: Add RTC I2C support for HP Core for esp32[-s2|-s3]
Add RTC I2C support for HP Core for esp32[-s2|-s3]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-01 14:16:55 -04:00
Eren Terzioglu
743b694560 arch/xtensa/esp32[-s2|-s3]: Add RTC I2C support
Add RTC I2C support for esp32[-s2|-s3]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-01 14:16:55 -04:00
Eren Terzioglu
36616025c7 arch/xtensa/esp32[-s2|-s3]: Add RTC GPIO write/read calls support
Add RTC GPIO write/read calls support for esp32[-s2|-s3]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-01 14:16:55 -04:00
Eren Terzioglu
b520655b07 arch/xtensa/esp32[-s2|-s3]: Add ULP RISC-V coprocessor support
Add ULP RISC-V coprocessor support for esp32[-s2|-s3]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-10-01 14:16:55 -04:00
guoshengyuan1
3f55710184 arch: remove nxsched_resume_scheduler in cpustart
Idle thread initialization does not require calling nxsched_resume_scheduler

Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
2025-09-30 23:26:28 +08:00
Filipe Cavalcanti
2e39707f3a arch/xtensa/espressif: fix Wi-Fi netpkt copy error
Fix an issue where netpkt copy would fail due to wrong
return checking condition.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-29 17:36:10 -04:00
guoshengyuan1
ca7608c2ac sched/irq: add a check for the interrupt stack in irq_dispatch
After irq_dispatch finished, the interrupt stack will be checked to
determine whether overflow occurs.
The relevant configuration reuses the configuration of stack overflow
detection during context switching.

Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
2025-09-29 19:12:18 +08:00
Matteo Golin
504ec6b2c6 arch/udelay: Make common, weak definition of up_*delay functions
Many different architectures re-implemented the exact same code for
`up_*delay` because it was originally written as architecture dependent
code. Busy-waiting can be done regardless of architecture, so this
commit moves that duplicated implementation to a common file with weak
definitions so that individual architectures (see tc32) are still able
to override the definition if needed/desired.

Default implementation is not included if ARCH_TIMER is enabled, since
it is more accurate and provides its own weak definitions to override.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2025-09-29 09:22:56 +08:00
guoshengyuan1
5d7ac216f2 arch: optimize up_check_tcbstack for stack overflow detection
Many times, context switching does not occur when the thread stack
memory is almost exhausted, so we need to mofify up_check_tcbstack to
accurately detect it.

Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
2025-09-27 12:56:11 +08:00
guoshengyuan1
6a57c56925 arch: replace all nxsched_suspend/resume_*** with nxsched_switch_context
Complete the missing scheduling information in some architectures

In these architectures (riscv, avr, tricor) context switching
can occur in both up_switch_context and xx_doirq

Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
2025-09-25 16:40:23 +08:00
Huang Qi
6f3658fe23 arch/xtensa: espressif: temperature: Fix incorrect pointer casting
Fix bug in temperature sensor driver where direct casting of lower half
structure pointer could lead to incorrect memory access.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2025-09-20 08:01:21 -03:00
wangchengdong
b92e0b6730 arch: fix alignment bug for archs that need stack alignment
These archs only align the size of the stack, forgeting to do the
 stack start addr alignment, this patch fixes it.

Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
2025-09-18 11:11:32 -03:00
Filipe Cavalcanti
662c1e0bbb boards/xtensa: update board and defconfigs for Wi-Fi on ESP32|S2|S3
Updates the defconfigs and board source to support driver refactor.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-14 10:41:15 +08:00
Filipe Cavalcanti
20ff68bd65 arch/xtensa: refactor Wi-Fi driver for ESP32|S2|S3
Fixes low and inconsistent bandwidth issues.
Adds new configuration options for buffer management.
Moves code around to make the implementation cleaner and easier to debug.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-14 10:41:15 +08:00
nuttxs
a5b810bdb1 Kconfig: Add configurable Stack Canaries protection levels.
Introduce a configurable stack-protection level for the existing
CONFIG_STACK_CANARIES, instead of hard-coding -fstack-protector-all.
Add Kconfig choice STACK_CANARIES_LEVEL four selectable levels:

 -fstack-protector
 -fstack-protector-strong
 -fstack-protector-all (default)
 -fstack-protector-explicit

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-09-11 19:56:42 +08:00
Filipe Cavalcanti
ed751889de arch/xtensa/esp32: Update E-Fuse driver
Updates E-Fuse driver for ESP32, now sharing a common implementation across Xtensa devices.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-06 14:46:32 -03:00
Filipe Cavalcanti
65d5f9bc8f arch/xtensa/esp32s2: Update E-Fuse driver
Updates E-Fuse driver for ESP32S2, sharing a common implementation for Xtensa devices.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-06 14:46:32 -03:00
Filipe Cavalcanti
23faaa29f7 arch/xtensa/esp32s3: Update E-Fuse driver
Updates E-Fuse driver for ESP32S3, now sharing a common implementation across
Xtensa devices.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-06 14:46:32 -03:00
Filipe Cavalcanti
d5f674d967 arch/xtensa: add common driver for E-Fuse on Espressif devices
Adds a common E-Fuse driver to be used by Espressif Xtensa devices.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-06 14:46:32 -03:00
Filipe Cavalcanti
1d51cfbda7 arch/xtensa: add sys_startup_fn call
Adds SYS_STARTUP_FN which calls constructors and init functions on
common source code. Requires compatibility changes on linker script.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-09-06 14:46:32 -03:00
Thiago Finelon
e87c43b798 arch/xtensa/esp32s3: Add EXT1 wakeup support in power management
Introduce EXT1 wakeup functionality to the ESP32-S3 power management
subsystem. With this feature, the ESP32-S3 can wake up from PM_STANDBY
or PM_SLEEP when one or more RTC GPIOs trigger the EXT1 condition.

Changes include:
- Added EXT1 wakeup configuration and preparation logic in rtc code.
- Integrated EXT1 handling in pmstandby() and pmsleep().
- New board-level Kconfig options under ESP32-S3 DevKit menu:
  - CONFIG_PM_EXT1_WAKEUP: enable EXT1 wakeup support
  - CONFIG_PM_EXT1_WAKEUP_RTC_GPIO<n>: select RTC GPIOs as wake sources
  - CONFIG_PM_EXT1_WAKEUP_TRIGGER_MODE: choose wakeup on HIGH or LOW level
- Fixing Kconfig style
- Fixing comments standard
- Adding PM documentation for esp32s3-devkit

Impact:
- No build impact unless CONFIG_PM_EXT1_WAKEUP is enabled.
- When enabled, ESP32-S3 can wake from low-power states via RTC GPIOs.
- No new public API introduced; controlled via board Kconfig.

Tested on ESP32-S3 DevKit:
- Configured GPIO4 and GPIO5 as EXT1 wake sources.
- Verified wakeup from light sleep and deep sleep on external signals.
- Wakeup reason correctly reported as EXT1.

Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
2025-08-24 11:32:10 -03:00
Jukka Laitinen
80cb2cf9c6 arch/xtensa/esp32,esp32s3: Start the "spiflash_op" thread with correct affinity
Set the affinity of the task before activating it. There is no parameter
or other interface in "kthread_create" to set the affinity mask,
like in "pthread_create".

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-22 15:46:47 -03:00
nuttxs
46bbde02b1 esp32/esp32_spiflash.c: during the SPI Flash erasure operation, task
scheduling (yield) is added to prevent the Watchdog Timer from
triggering a reset due to timeout

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-08-22 20:47:03 +08:00
nuttxs
0ff26f0850 esp32/esp32_partition.c: based on the latest revision, in the ESP32 compilation
environment, uint32_t is defined as long unsigned int (i.e., unsigned long)

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-08-22 00:26:46 +08:00
Tiago Medicci Serrano
d250808c1c esp32s3/elf: Fix ELF loader on ESP32-S3 when using external PSRAM
Prior to this commit, it wasn't possible to load ELF modules from
the external PSRAM. There were two main issues about it: 1) copying
data using the instruction bus was being used instead of the data
bus (this, per si, isn't a problem, but requires special attention
regarding data alignment), and 2) the cache was not being properly
cleaned and flushed to properly access the loaded data using the
instruction bus.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-08-20 02:23:03 +08:00
Tiago Medicci Serrano
60ca804b56 esp32s3: Fix bug related to the PSRAM-allocated task stack
If both SPI Flash support (`CONFIG_ESP32S3_SPIFLASH`) and PSRAM
(`CONFIG_ESP32S3_SPIRAM`) are enabled, the PSRAM can only be
assigned to the user's heap (`CONFIG_ESP32S3_SPIRAM_USER_HEAP`).
Additionaly, `CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK` must be
set because the system will end up allocating tasks' stacks from
the external PSRAM. This has an impact when dealing with SPI flash
operations because the cache must be disabled and the running task
should not rely on any data from the PSRAM. To accomplish that, It
offloads the SPI flash operation to a work queue (which, by
definition, allocates its heap from the kernel heap).

The same (assigning the PSRAM to the user's heap) is valid when the
Wi-Fi is enabled because the lower-half driver requires data being
allocated from the internal memory (which can only be achieved by
allocating from the kernel heap when both the kernel and user heaps
exists).

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-08-20 02:23:03 +08:00
Stepan Pressl
637f15ff3c Make/Toolchain.defs: add the AR_EXTRACT command
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.

Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
2025-08-19 09:47:44 +08:00
Eren Terzioglu
21787b49f0 arch/xtensa/esp32s2: Remove duplicated lines to fix warning
Remove duplicated lines to fix build warning for esp32s2

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-08-16 08:41:18 -03:00
Jukka Laitinen
50d94863f2 arch/xtensa: Fix a race condition in xtensa_sig_deliver for SMP
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[REG_PS]) will enable them if they were
enabled in the context.

Any interrupt on this cpu before xtensa_context_restore() would set
the rtcb->xcp.regs to NULL, causing a crash in context restore.

Fix this by calling leave_critical_section(up_irq_save()) instead.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-01 08:54:39 -03:00
YAMAMOTO Takashi
69bcbfb207 esp32s3_extraheaps.c: add a missing include for xtensa_imm_initialize
Signed-off-by: YAMAMOTO Takashi <yamamoto@midokura.com>
2025-07-25 15:51:38 +08:00
Martin Vajnar
150854c6f2 ESP_PCNT: add high and low limit Kconfig options
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
2025-07-22 13:09:02 -03:00
Filipe Cavalcanti
a7cd6bb401 arch/xtensa: add E-Fuse support on ESP32S2
Adds support for e-fuse on ESP32S2 and fixes a gitignore issue.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-22 10:55:08 -03:00
chao an
9e53aab5b3 xtensa/isa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
common/xtensa_context.S: Assembler messages:
common/xtensa_context.S:134: Error: invalid register number (231) for 'rur' instruction
common/xtensa_context.S:283: Error: invalid register number (231) for 'wur' instruction
clang-10: error: Xtensa-as command failed with exit code 1 (use -v to see invocation)
make[1]: *** [Makefile:143: xtensa_context.o] Error 1
make[1]: *** Waiting for unfinished jobs....

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-07-21 12:56:31 +02:00
nuttxs
d1fababfc5 arch/xtensa: esp32(s3)_async_op() using nxsem_wait(), threads may
return early due to signal interruption (EINTR). This makes the
main thread think the async operation is done, but the background
worker thread is still running—risking access to freed memory,
race conditions, crashes or undefined behavior.

Using nxsem_wait_uninterruptible():the main thread waits until the
worker thread finishes, preventing these issues.

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-07-18 22:34:13 +08:00
Eren Terzioglu
af8e43e7f2 arch/xtensa: Bugfix I2C Slave build error for esp32[-|-s2|-s3]
Fix build error for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-09 12:18:06 +08:00
Eren Terzioglu
2e4eaf69ee arch/xtensa: Add arch layer SHA accelerator support for esp32[-s2|-s3]
Add arch layer SHA accelerator support for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-09 12:13:06 +08:00
Eren Terzioglu
735e16f842 arch/xtensa: Fix dedicated GPIO build error
Fix dedicated GPIO build error for esp32[-s2|-s3]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-08 11:58:15 +08:00
Eren Terzioglu
5991a8c4cc xtensa/espressif: Change LEDC implementation to common for Xtensa based Espressif chips
Change LEDC implementation to common one for esp32[-s2|-s3]

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-05 11:12:06 +08:00