Updates the SPI Flash driver used for user storage MTD.
Updates board linker script and bring up.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The nxsched_switch_context() function should only be called
when a task switch actually occurs. The RISC-V architecture
already performs this call in riscv_perform_syscall(),
so this PR removed the redundant nxsched_switch_context() call in
up_switch_context().
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Updates the common source code for the SPI peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit refactors the I2S common driver for Espressif's RISC-V
SoCs. Previously, the peripheral was not working as expected.
Along with the new I2S character driver, this new I2S lower-half
driver can be easily tested using internal loopback between the
transmitter and receiver channels.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
E51 needs to use vendor specific CSR to enable L1 cache.
This adds the relevant register setting and makes it
configurable by CONFIG_MPFS_E51_ENABLE_CACHE. With this flag set, the L2
cache on E51 depends on the cache lane configuration. Disabling this flag
disables all caches on E51.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This adds a header file, defining microchip's vendor specific
CSR registers for E51 monitor core on MPFS SoC
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Updates the common source code for the LEDC peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the SHA accelerator used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the GPIO peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the PCNT peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the MCPWM peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
After irq_dispatch finished, the interrupt stack will be checked to
determine whether overflow occurs.
The relevant configuration reuses the configuration of stack overflow
detection during context switching.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Many different architectures re-implemented the exact same code for
`up_*delay` because it was originally written as architecture dependent
code. Busy-waiting can be done regardless of architecture, so this
commit moves that duplicated implementation to a common file with weak
definitions so that individual architectures (see tc32) are still able
to override the definition if needed/desired.
Default implementation is not included if ARCH_TIMER is enabled, since
it is more accurate and provides its own weak definitions to override.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Updates the common source code for the I2C peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Many times, context switching does not occur when the thread stack
memory is almost exhausted, so we need to mofify up_check_tcbstack to
accurately detect it.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Complete the missing scheduling information in some architectures
In these architectures (riscv, avr, tricor) context switching
can occur in both up_switch_context and xx_doirq
Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Updates the common source code for the UART peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the RMT peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the twai peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
The Kconfig entry `ESPRESSIF_ESP32[C3|C6|H2]` can be removed as the
already existing `ARCH_CHIP_ESP32[C3_GENERIC|C6|H2`] fulfills its
purpose completely.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Fix bug in temperature sensor driver where direct casting of lower half
structure pointer could lead to incorrect memory access.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit updates the common source code for the timers used for
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
These archs only align the size of the stack, forgeting to do the
stack start addr alignment, this patch fixes it.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
This commit fixes E-Fuse driver to get proper block and bit offset.
Also adds support for virtual and flash E-Fuses.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Fixes low and inconsistent bandwidth issues.
Adds new configuration options for buffer management.
Moves code around to make the implementation cleaner and easier to debug.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
This removes the need to have all the DDR/clock configuration related
"LIBERODEFS" flags defined, when not building a standalone/coldboot
configuration
All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
The interrupt handler accesses the device as well as the driver's private
data. Thus, must take the big kernel lock in SMP mode to protect them.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
In SMP mode one CPU can be executing the MMC interrupt while another CPU
disables (e.g. via watchdog timeout). As it is disabled the other CPU
assumes it's safe to start configuring the device after this.
This causes a leak in the driver's private data as well as a mutual
exclusion leak on the device itself.
Fix this by aborting any triggered interrupt by checking whether it's
even enabled.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
Currently the irq handler checks many reserved bits, which is
a waste of resources:
1. pending_rx_ep bit 0 is reserved (always 0)
2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4
defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the
rest are reserved
Fix this by checking only the relevant bits.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
As emmcsd driver does not support separate WRCOMPLETE interrupt the
SDIOWAIT_WRCOMPLETE event shall not be waited.
The SDIOWAIT_TRANSFERDONE event indicates that both "transfer done"
and "write complete" events are completed.
mpfs_sendcmd() shall not wait for data lines ready before
sending commands to the card. This prevents mmcsd driver
to poll card busy status prior to next activity after
a write operation.
