This function can identify (during the runtime) whether the chip
is revB or revA. Bear in mind PIC32CZ2051CA70 is always revB.
Allows to have one binary compatible with SAMV7 and PIC32.
Thanks to Pavel Pisa and Michal Lenc for the suggested code.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
SAME70J and SAMV70J series (64 pin packages) have two USART peripherals
and three UART peripherals. Ensure USART peripherals are enabled.
This is consistent with datasheet, USART0 also physically tested
on SAME70J21 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The following warning occurred if ARCH_CHIP_PIC32CZCA70 option was
selected. The variable is not used in case of PIC32CZ CA70 series.
CC: task/task_getgroup.c chip/sam_emac.c: In function ‘sam_emac_initialize’:
chip/sam_emac.c:4758:12: warning: unused variable ‘regval’ [-Wunused-variable]
4758 | uint32_t regval;
|
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
PIC32CZ CA70 family is pin to pin and binary compatible with
SAMV70/SAME70 families, therefore the support is placed in samv7
directory. The only difference is larger RAM memory compared to SAM
families.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
__start should call up_perf_init, initialization of hardware performance
counter, if CONFIG_ARCH_PERF_EVENTS option is set. This allows the
usage of ARM cycle count register DWT_CYCCNT in benchmark
measurements instead of software clock.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Bitfield CPHA has to be set to run SPI in mode 0. This is a default mode,
therefore it should be set during the peripheral initialization.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Interrupts should be disabled during the access to the user signature
area in internal flash memory, otherwise the system might be halted.
This applies also for read operation as this is performed with a
special flash commands on a special part of memory.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
GPIO peripheral clocks have to be enabled even if interrupt support
on the peripheral is not enabled, otherwise GPIO input will not work.
This is probably caused by input filters that need clock signal.
This commit moves the clock enable call from interrupt specific function
to common initialization function that is called from _start entry
point function.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add no_builtin for memcpy/memset to the startup code of boards
with CONFIG_ARCH_RAMFUNCS, because certain compilers call memcpy/memset
instead of the explicit for loop. This will cause a crash if memcpy/memset
are mapped to RAM because the function that copies them to RAM is called later,
resulting in undefined code being executed.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
arch/arm: Use decorator for entry point
Use a decorator that contains the required no_builtin instead of adding
them explicitly to the startup code. This way it will be easier to
maintain them in the future when changes to the no_builtin used are required.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
arch/arm: Rename decorator
Rename the entry point decorator used for the startup code to a less explicit name.
This way the style is more consistent with other decorators.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
ifdelay description (delay between frames) matches the DLYBCT field
(delay between consecutive transfers without removing chip select)
much better compared to stopdelay (delay between last CLK and CS
innactive). The option for stopdelay does not seem to be configurable
in SAMv7 peripheral.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
DTE (dead time enable) is the 17th bit in CMRx (channel mode) register.
Function pwm_set_polarity did however read and write this register as
16 bit large, therefore dead time generation was always disabled.
This fixes the issue, pwm_set_polarity now reads the register as 32
large.
Also set the initial value of CMRx correctly in pwm_setup().
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds configuration option for every fault input, that can be
latched (kept even after the input value is below the threshold) or
volatile (PWM is automatically enabled once the output polarity goes
back to the normal state).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
chip/sam_1wire.c:921:7: warning: implicit declaration of function 'sam_usart0_enableclk' [-Wimplicit-function-declaration]
921 | sam_usart0_enableclk();
The same warning applied for other uart/usart peripherals configured
as 1 wire.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The message RAM does not behave correctly if lower 16 bits of
buffer address overflow (upper 16 bits are set once in matrix driver
for the entire CAN driver). For example message RAM starting at
0x2040fc20 would not work for buffers that go beyond 0x20410000 and
MCAN would sent data located at 0x20400000 to the network. The same
issue would occur even if TX buffers would start directly at 0x20410000.
The upper 16 bits would still have 0x2040 value because of RX buffers
located in 0x2040ffff range.
This commit ensures the RAM is always located at the beginning of
the data section and thus the overflow mentioned above should never occur.
The alternative would be to use larger alignment, but the message RAM
can have up to 4352 words and this would cause a significant padding.
The RAM is also initialized to zero to ensure valid parity/ECC checksums.
The address issue is not described anywhere in the manual, so it is
possible this is caused by some incorrect configuration, but the context
of the registers looks valid.
This commit also fixes the compilation errors when the driver is run
without data cache.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The CPCSTOP has a negative effect on the periodic timer operation.
This causes the timer to stop when an overrun occurs.
Timer must be then restarted in the interrupt. However, as interrupts
are not infinitely fast, this prolongs the next timeout.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
So far only USART drivers could use TX/RX DMA. This commit adds the
support for UART drivers as well (with the exception of serial console).
UART peripheral does not have timeout interrupt, so external polling
is required to flush the RX data from DMA buffers even if the buffer
is not yet full. The board layer can do this by calling
sam_serial_dma_poll function.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
ADC peripheral can be configured also for PWM trigger, so the ifdef
should depend only on CONFIG_SAMV7_AFEC_SWTRIG. Also handle the
situation when ANIOC_TRIGGER is called and the peripheral is not
configured for SW trigger (but the other one may be, so config option
is set).
Trigger values saved to the private structure are also changed to
enums for better code clarity.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
reason:
We decouple semcount from business logic
by using an independent counting variable,
which allows us to remove critical sections in many cases.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
svc call may trigger hardfault
Background
The origin of this issue is our desire to eliminate the function of storing
"regs" in g_current_regs and instead utilize (*running_task)->xcp.regs for storage.
The benefits of this approach include faster storage speed and
avoiding multiple accesses to g_current_regs during context switching,
thus ensuring that whether returning from an interrupt or an exception,
we consistently use this_task()->xcp.regs
Issue Encountered
However, when storing registers, we must ensure that (running_task)->xcp.regs is invalid
so that it can be safely overwritten.
According to the existing logic, the only scenario where (running_task)->xcp.regs
is valid is during restore_context. We must accurately identify this scenario.
Initially, we used the condition (running_task)==NULL for this purpose, but we deemed
this approach unsatisfactory as it did not align well with the actual logic.
(running_task) should not be NULL. Consequently, we adopted other arch-specific methods for judgment,
but due to special logic in some arch, the judgment was not accurate, leading to this issue.
Solution:
For armv6-m, we haven't found a more suitable solution, so we are sticking with (*running_task)==NULL.
For armv7-m/armv8-m, by removing support for primask, we can achieve accurate judgment.
PRIMASK is a design in armv6-m, that's why arm introduce BASEPRI from armv7-m.
It's wrong to provide this option for armv7-m/armv8-m arch.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
EEFC read sequence requires read length in words instead of bytes,
therefore bytes given by the user has to be recalculated to words.
The calculation however had a mistake in brackets and was just adding
1 to buflen instead of recalculating it to 4 byte words. This caused
global array g_page_buffer to overflow for some reads.
This fixes the calculation.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds a max_pins field into the private struct.
AFEC0 has 11, AFEC1 has 12. The 12th pin of AFEC0 is an internal
pin connected to a temperature sensor, which we don't use.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
Commit 313d6df7 caused the following build error:
CC: fixedmath/lib_b16atan2.c chip/sam_qspi.c: In function 'qspi_memory':
chip/sam_qspi.c:1552:7: warning: implicit declaration of function 'IS_ALIGNED' [-Wimplicit-function-declaration]
1552 | IS_ALIGNED((uintptr_t)meminfo->buffer, 4) &&
| ^~~~~~~~~~
In file included from chip/sam_qspi.c:41:
chip/sam_qspi.c: In function 'qspi_alloc':
chip/sam_qspi.c:1591:21: warning: implicit declaration of function 'ALIGN_UP' [-Wimplicit-function-declaration]
1591 | return kmm_malloc(ALIGN_UP(buflen, 4));
This was caused by missing include of nuttx.h header defining ALIGN_UP
and IS_ALIGNED.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
