By default, the full configured DTCM region is assigned to the heap for
dynamic allocation. In scenarios requiring deterministic memory regions
for static buffers or control structures, you can reduce the heap
allocation to reserve part of DTCM for manual/static use.
This kconfig symbol allows to limit the size.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The adc_dmaconvcallback routine was far too slow and inefficient. This was not caught until recently when I was testing faster sample rates. When in circular mode for the adc (dma and constant conversions), the adc_dmaconvcallback function would overwhelm the OS and lock it up. I looked into this and did a lot of testing. First I tried minimally improving the dma callback by removing the % operator from the algorithm, this was slow and inefficient. I also tried increasing the batch size considerably as well as the fifo size. This helped but the OS would still lockup with the fastest sample rate (5 Msps). au_receive_batch was the solution. In order to use this, I needed to change the dmabuffer to be of type uint32_t to match the data pointer in au_receive_batch. I also needed to create a channel buffer, which is initialized once in adc_setup. stm32_gpdma_cfg_s->tr1 needed to be updated for the uint32_t dmabuffer. Once I made changes to use au_receive_batch, I could reliably use the fastest sample rate without locking up the OS. Calling au_receive for every single conversion in a batch is far less efficient than calling au_receive_batch. I also snuck in some changes for the ADC watchdog defines and guards. These were fixes that were tested while testing these changes.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
This function can identify (during the runtime) whether the chip
is revB or revA. Bear in mind PIC32CZ2051CA70 is always revB.
Allows to have one binary compatible with SAMV7 and PIC32.
Thanks to Pavel Pisa and Michal Lenc for the suggested code.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
Previously the function "up_cpu_pause" was used for preventing all other
CPUs from executing code from flash.
The above function was removed in d8cb7759.
Now flash operations work on rp2040 in SMP mode by blocking all but the
current CPU for the duration of the critical function (write or erase).
Closes: #16203
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
Adding the stm32h5 pwm driver. This is almost an exact copy of the stm32h7 pwm driver. I confirmed the timers for the h5 are version v2 and added the preprocessor definition. This commit was tested on a stm32h5 nucleo-h563zi development board. Necessary board files and a pwm config have been added. Added pin mappings for all timer outputs.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
Added documentation regarding nucleo-h563zi:pwm config.
Removed CONFIG_STM32H5_PWM guard at the top. Fixed IRQs for tim1 and tim8. Added H5 to list of Timer IP v2 timers.
Conditionally compile stm32_serial.c.
Add stm32_pwm.c to CMakeLists.txt
When closing a serial port an ongoing TX DMA transfer will be stopped. This can cause
one (or multiple) the following:
- dev->dmatx.length != 0
- dev->dmatx.nlength != 0
- stm32_dmaresidual returning a non-zero residual
This is caused by length/nlength not being set to 0 at startup or during closing.
In addition the DMA_SxNDTR register is not set to 0 at startup or during closing.
This commit solves the issue by setting the variables and register to 0 during closing.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
arch/arm/stm32h7: Add review feedback regarding style
Removed non-needed spaces.
Aligned style of documentation.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
When SEMIHOST_SYSLOG is enabled it creates its own up_putc() function
however the stm32_serial.c also creates this same function, even
when all STM32_USARTs are disabled. Fix patch fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Remove the comment which is copy-paste from stm32/stm32_eth.c.
stm3240g-eval doesn't contain any valuable information about eth driver.
If we need to find an explanation of the configuration options, they are in
Kconfig files.
Signed-off-by: raiden00pl <raiden00@railab.me>
clock_systime_timespec() always returns 0, so there is no need to
check the return value in the caller code, let us remove the return
value directly.
Signed-off-by: chao an <anchao.archer@bytedance.com>
Add FLASH support for STM32C0 based on STM32G0 FLASH driver.
FLASH support is identical for these two, except that the STM32G0 can support
dual bank, which is not available in the STM32C0.
Signed-off-by: raiden00pl <raiden00@railab.me>
PWR is not supported for STM32C0 yet, fix build error when CONFIG_STM32F0L0G0_PWR=y
which is required to access backup registers (we need enable PWR clock for this).
Signed-off-by: raiden00pl <raiden00@railab.me>
update STM32C0 PWR registers:
- there is no F,G,H and I GPIOs, so we can remove some registers
- add definitions for PWR backup registers
Signed-off-by: raiden00pl <raiden00@railab.me>
After irq_dispatch finished, the interrupt stack will be checked to
determine whether overflow occurs.
The relevant configuration reuses the configuration of stack overflow
detection during context switching.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Many different architectures re-implemented the exact same code for
`up_*delay` because it was originally written as architecture dependent
code. Busy-waiting can be done regardless of architecture, so this
commit moves that duplicated implementation to a common file with weak
definitions so that individual architectures (see tc32) are still able
to override the definition if needed/desired.
Default implementation is not included if ARCH_TIMER is enabled, since
it is more accurate and provides its own weak definitions to override.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Many times, context switching does not occur when the thread stack
memory is almost exhausted, so we need to mofify up_check_tcbstack to
accurately detect it.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Added ioctls and functions for watchdogs 2 & 3. Modifed wdog1 functions. Needs testing.
Fixed issues with started variable.
Change to add only 3 ioctls, a config for each watchdog. Created cfg structures for watchdog1 and watchdog23. Added code to set difsel register. stop conversions before changing watchdog configs. Other logic changes.
Define AN_STM32H5_FIRST and AN_STM32H5_NCMDS in nuttx/analog/ioctl.h
Remove hardcoded AN_STM32H5_FIRST.
Style fixes.
Fix thershold for watchdog1
Got working watchdog driver with queue and signal. Needs polish.
Refined isr for watchdogs. Added value back to event. value is more accurate, but not guaranteed. It accomdates dma.
Used stm32_adc_sigcfg_s structure inside stm32_adc_sig_s structure. Used common naming for ioctls.
Added stopifstarted and startifstopped for setting watchdogs and other bits. Added adc_reset_dma, which must be run after stopping conversions in circular mode, because buffer and conversions become misaligned. Other refinements.
Added guard around adc_reset_dma, added comment blocks to new functions
NuttX style fixes.
Add return value to wdog configure functions.
Correct number of stm32h5 adc ioctls.
Minor style fix.
Reduce watchdog commit to fit NuttX standards. Remove Queue and Signal aspects. Added Kconfig to initialize watchdog.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
Added guard around code referencing priv->circular. Added adc_watchdog config for testing watchdog1 with adc1. Added documentation about adc_watchdog config.
Adjusted documentation for adc_watchdog config. Added detailed test procedure.
Longer underline under adc_watchdog title.
Add code for differential adc calibration. Need to calibrate both single-ended and differential if a given adc has both single-ended and differential channels.
Fixed typo.
Initialize watchdog1 parameters at compile time when configured. Added comments to new elements in stm32_dev_s. Confirmed style is good.
Add proper guards around ADC WDG1 variables and functions.
Implemented feedback per raiden00. 1. Changed to use old chanlist type uint8_t. 2. Added smpr1, smpr2, and difsel variables to stm32_dev_s structure. 2. smpr1 and smpr2 are initialized to board defined values if BOARD_ADCx_SMPRx is defined, otherwise initialized to default. 3. difsel initialized to BOARD_ADCx_DIFSEL if defined, otherwise use default (0) for all single-ended.
The arm-m architecture svc call will trigger an interrupt,
and the actual context switch is executed after doirq is completed,
so only the scheduling information needs to be updated in doirq.
In the arm-a/r architecture, interrupts and syscalls are independent,
and scheduling information needs to be updated in both locations
Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Currently the mdio communication is part of the monolithic 'full netdevs'.
This commit serves as an way to add modularity for the netdevs drivers.
A new upperhalf/lowerhalf mdio device comes with this commit that manages the data transfer ofer mdio interface.
Signed-off-by: Luchian Mihai <luchiann.mihai@gmail.com>
- Created a file rp2040_common_pico.h with function
prototype
int rp2040_dev_gpio_init(void);
to allow cmake + ninja to build without errors.
- Updated file rp2040_pico.h with
for all boards.
Signed-off-by: simbit18 <simbit18@gmail.com>
- CMake added board Raspberry Pi Pico
- Added the entry:
CMake,raspberrypi-pico:bmp280
to the file arm-06.dat.
- Moved the search for the Python 3 interpreter to the
root CMakefile to avoid unnecessary repetition.
Signed-off-by: simbit18 <simbit18@gmail.com>
Add STM32H7_STM32H7X0XX chip family.
Add new chip configurations for STM32H750 variants in Kconfig, update
hardware includes to support CONFIG_STM32H7_STM32H7X0XX, and modify
board configurations for stm32h750b-dk to use STM32H750XB.
This enables support for the new STM32H750 chip series with appropriate
memory and peripheral mappings.
Normalize the defconfig files for boards from stm32f7 chip family.
Signed-off-by: Sergey Rzhevsky <rzsa@yandex.ru>
This patch addresses several issues and adds enhancements to the WWDG
(Window Watchdog) implementation for the STM32H7 platform. The changes
include:
- Extend the definitions of WWDG_CFR_PCLK1 macros to support dividers
up to 128, and update the stm32_settimeout() function to consider this
extended range.
- Fix the "elapsed" calculations in the stm32_getstatus() function to
ensure correct time remaining calculations.
- Clear the EWIF (Early Wakeup Interrupt Flag) bit in the stm32_start()
function, as this bit might be set by hardware before the watchdog is
actually started.
- Initialize the WWDG clock in the RCC_APB3ENR register and set the
RCC_GCR_WW1RSC bit as per the STM32 reference manual to ensure proper
behavior when enabling the WWDG1.
Signed-off-by: Szymon Magrian <szymon.magrian@hexagon.com>
SAME70J and SAMV70J series (64 pin packages) have two USART peripherals
and three UART peripherals. Ensure USART peripherals are enabled.
This is consistent with datasheet, USART0 also physically tested
on SAME70J21 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Adds conditional compilation of the stm32_ltdc.c file to the source list
(SRCS) for STM32H7 architecture when the CONFIG_STM32H7_LTDC option is
enabled in the configuration.
Signed-off-by: Sergey Rzhevsky <rzsa@yandex.ru>
The stack alignment operation in tricore and arm porting
only aligns the size of the stack, forget to align the start addr
of the stack, this patch fixes it.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Since the alignment of the signal context is affected by XCPTCONTEXT_SIZE in
different Kconfig, sometimes the stack pointer is not aligned to 8 bytes, this
is not what the software and compiler expect, for example, if va_list() obtains
wide data of type long long, the offset will be wrong, So in this commit, we set
stack-aligned the base offset so that the correct offset will be set during context
restoration.
1. test code:
| void signal_handler(int signo, siginfo_t *info, void *context) {
| long long ttt = 1024000;
| printf("%lld\n", ttt);
| }
|
| struct itimerspec its = { .it_value.tv_sec = 1,
| .it_value.tv_nsec = 0,
| .it_interval.tv_sec = 1,
| .it_interval.tv_nsec = 0
| };
|
| int main(int argc, FAR char *argv[])
| {
| struct sigevent evp;
| timer_t timer_id;
|
| memset(&evp, 0, sizeof(evp));
| evp.sigev_notify = SIGEV_SIGNAL | SIGEV_THREAD_ID;
| evp.sigev_signo = SIGALRM;
| evp.sigev_notify_thread_id = gettid();
|
| timer_create(CLOCK_REALTIME, &evp, &timer_id);
|
|
| struct sigaction sa;
| memset(&sa, 0, sizeof(sa));
| sa.sa_sigaction = signal_handler;
| sa.sa_flags = SA_SIGINFO;
| sigemptyset(&sa.sa_mask);
|
| sigaction(SIGALRM, &sa, NULL);
|
| timer_settime(timer_id, 0, &its, NULL);
|
| while (1)
| sleep(1);
|
| return 0;
| }
2. before this change:
| NuttShell (NSH) NuttX-12.10.0
| nsh> hello
| 4398046527890440
| 4398046527890472
| 4398046527890504
| 4398046527890536
3. after this change:
| NuttShell (NSH) NuttX-12.10.0
| nsh> hello
| 1024000
| 1024000
| 1024000
| 1024000
Signed-off-by: chao an <anchao.archer@bytedance.com>
The functions `hw_write_masked` and `hw_xor_bits` (as defined in
pico-sdk) were defined in NuttX twice.
Additionally these definitions were in conflict (one lacked the
`volatile` modifier).
Now these functions and their dependencies are defined in a new header
file.
Its name is based on the filename of the original definition in
pico-sdk:
src/rp2_common/hardware_base/include/hardware/address_mapped.h
This change should fix the potential issue of GPIO operations failing
due to compiler optimizations caused by the absence of `volatile`.
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
On a system with multiple CPU cores, when the system is powered on,
multiple cores may start running simultaneously. In this case, software
is required to handle the startup logic for multi-core synchronization.
One approach is to use global variables.
however, the global variable region may not have been initialized yet.
In such scenarios, we can use a busywait flag to
implement the synchronization strategy.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
On a system with multiple CPU cores, when the system is powered on,
multiple cores may start running simultaneously. In this case, software
is required to handle the startup logic for multi-core synchronization.
One approach is to use global variables.
however, the global variable region may not have been initialized yet.
In such scenarios, we can use a busywait flag to
implement the synchronization strategy.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some iMXRT chips like iMXRT-1050 has two USB controllers, but until
now only USB1 was supported. This patch modify the driver to support
both USBs.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Give the user the full control over the USIC FIFO buffer even if USIC channel 0 is disabled.
When USICx_CHAN0 is not an UART but USICx_CHAN1 is, the user can set the desired FIFO buffer offsets in CHAN1 config.
Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Port of https://github.com/apache/nuttx/pull/16848
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
The following warning occurred if ARCH_CHIP_PIC32CZCA70 option was
selected. The variable is not used in case of PIC32CZ CA70 series.
CC: task/task_getgroup.c chip/sam_emac.c: In function ‘sam_emac_initialize’:
chip/sam_emac.c:4758:12: warning: unused variable ‘regval’ [-Wunused-variable]
4758 | uint32_t regval;
|
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
