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24187 commits

Author SHA1 Message Date
liwenxiang1
f858026819 arch/x86_64:Add allsymbol functionality 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 14:56:08 +08:00
Huang Qi
20cba94a86 risc-v/espressif: Fix alert message in esp_setup_irq() 
Correct the alert message in `esp_setup_irq()` if
irq number allocation fails, the parameter number is not
matched with format specifier.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-10-10 13:41:34 +08:00
liwenxiang1
e3b3a6145a arch/x86_64: idle convert all asm() to __asm__() 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 13:40:39 +08:00
liwenxiang1
1af831e139 arch/x86_64: cpuid expect 32 bit variables 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 12:03:27 +08:00
liwenxiang1
2448e8a59e arch/x86_64:Add perf tool 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 12:01:16 +08:00
liwenxiang1
f81c7dbc93 arch/x86_64:Use the checkstack function 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 11:40:15 +08:00
hujun5
e249dd2672 arch: support customized up_cpu_index() in AMP mode 
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
 2024-10-10 02:38:40 +08:00
ligd
ff99745b22 arm-m: support zero interrupt back to game 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
a9da6ab4b5 arm-M: set current regs for crash dump 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
780acd7827 armv6/7/8m: use pendsv to handle context switch 
This PR support Nested interrupt in armv6/7/8m:

There are two types of nested interrupt model:

Zero latency nested interrupt
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x50
High irq1           0x60             ISR can't access system API
irq_save()          0x70
High irq2           0x80             ISR can't access system API
normal irq3         0xB0
We have already support this mode before this PR

Nested interrupt which interrupt level lower than up_irq_save()
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x70
irq_save()          0x80
High irq1           0x90              ISR can access system API
High irq2           0xA0              ISR can access system API
normal irq3         0xB0
Now, this PR can support this mode

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
f221c9ecb4 armv6m: add up_trigger_irq() support 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
f20ae064b0 armv7/8m: unmask all the IRQ when thread start 
NVIC_SYSH_PRIORITY_MIN not the basepri loweest prio
spec says:
basepri 0 - Disables masking by BASEPRI

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
liwenxiang1
4c19e75ff5 libs/x86_64:Add the setjmp/longjmp function 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 22:24:03 +08:00
wangmingrong1
47fc3a67f7 sim/kconfig: delete non-existent dependencie 
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
 2024-10-09 21:27:47 +08:00
yinshengkai
034af29aab arch: adjust gcov configuration name 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-09 21:27:47 +08:00
liwenxiang1
8fe6c0ee8e arch/x86_64: Map the new page table with read-write permissions 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 20:51:58 +08:00
Filipe Cavalcanti
42b7097cc2 xtensa/esp32s3: fix missing peripheral initialization for watchdog timer 2024-10-09 20:49:48 +08:00
liwenxiang1
eb411101c5 arch/x86_64:Configure arch delay using CONFIG_ALARM_ARCH 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 20:49:19 +08:00
ligd
784937a03c arm64: fix backtrace failed 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
Bowen Wang
f172f222be arm64_checkstack: fix crash, optimize the stack color, sync with arm 
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
wangming9
3054b1ad51 arch/arm64: Fixed arm64_cache_get_info obtaining cache. 
Summary:
Select icache or dcache by setting register csselr_el1.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
wangming9
cb62c783a9 arch/arm64: Add the interface for icache and dcache. 
Summary:
Add up_get_icache_size、up_invalidate_icache、up_get_dcache_size

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 20:47:43 +08:00
wangmingrong1
0866010101 arm64/makefile: No longer using hwasan pile insertion 
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
 2024-10-09 18:15:13 +08:00
ligd
26dc3b297a arm64: exclude mpu from sanitize for SMP mode 
CPU0 boot -> mm_init() -> sannitize on -> boot other CPUs
CPU1 boot -> mpu_init -> error

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 18:15:13 +08:00
ligd
e9617583bc arm64-r/mpu: add TBI setting to r82 when use SW_TAG 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 18:15:13 +08:00
yinshengkai
73d9a1b4a2 sim: disable sim uart output processing 
Using the host serial port to send data in sim will convert \r to \r\n

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-09 18:13:46 +08:00
raiden00pl
e419d2c392 arch/arm/Kconfig: fix copy-paste error 
ARCH_CHIP_CSK6 has nothing to do with ST chips:
fix option string and move below ST related options
 2024-10-09 18:11:20 +08:00
liwenxiang1
8b86f5de60 arch/x86_64: add support for thread_local 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 17:58:01 +08:00
liwenxiang1
5e15fff58a arch/x68_64: properly align ap boot stack for vector operations 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 17:40:37 +08:00
liwenxiang1
b4c4cbc28b arch/x86_64: Resolve weak symbol compilation relocation errors 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 17:39:42 +08:00
lipengfei28
56495bc9ce The gicv2m spinlock init status should unlocked 
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
 2024-10-09 15:07:37 +08:00
hujun5
17ca45e8a3 sim: fix sim smp boot regression 
This commit fixes the regression from https://github.com/apache/nuttx/pull/13716

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-09 12:33:21 +08:00
Xiang Xiao
b068e2357a circbuf: Move from mm/circbuf to libs/libc/misc 
so that it can be used by userspace program.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
 2024-10-09 08:41:49 +08:00
chenzhijia
a443a37390 drivers/coresight:ETM4 setup 
Signed-off-by: chenzhijia <chenzhijia@xiaomi.com>
 2024-10-09 08:37:48 +08:00
ligd
6dc08ee681 pci: fix compile failed, fdt_get_reg_base() need 3 args 
goldfish: fix compile failed, fdt_get_irq_by_path() need 4 args

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-09 02:18:49 +08:00
liwenxiang1
cd03ec3266 arch/x86_64:Add check stack function 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 01:53:09 +08:00
liwenxiang1
afe1cc59b6 arch/x86_64: Add vfork support 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 01:41:35 +08:00
anjiahao
9ed93c6b1e unify MODULE & ELF flag to Toolchain.defs 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2024-10-08 19:56:33 +08:00
Ville Juven
e5aef873a2 riscv_internal.h: Remove riscv_sbi.h from the file 
riscv_internal.h is used literally everywhere, while the SBI definitions
are needed only by whomever needs the services.

Having the SBI definitions:
a) Copied from OpenSBI (why has this been done? even the names are same)
b) Presented publicly to 99% of risc-v modules

creates a build error when building with OpenSBI, due to duplicate
definitions of the SBI service identifiers:

In file included from /nuttx/arch/risc-v/src/common/riscv_internal.h:40,
                 from /nuttx/arch/risc-v/src/chip/chip.h:32,
                 from board/mpfs_domain.c:30:
/nuttx/arch/risc-v/src/common/riscv_sbi.h:36: error: "SBI_EXT_BASE" redefined [-Werror]
   36 | #define SBI_EXT_BASE            0x00000010

and so forth...

Fix this by removing riscv_sbi.h i.e. not exposing the ABI publicly.
 2024-10-08 19:55:53 +08:00
yinshengkai
f26ae83900 arch/irq: add the up_getusrpc macro to get the PC of the interrupted thread in the interrupt 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 19:55:28 +08:00
hujun5
99b364c880 x86_64: fix regression 
This commit fixes the regression from https://github.com/apache/nuttx/pull/13768

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-08 15:27:57 +08:00
buxiasen
a6b12eb29c goldfinsh: fix timer compile issue 
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
 2024-10-08 15:27:33 +08:00
ligd
e7094ec40a goldfish: use goldfish timer 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 15:27:33 +08:00
buxiasen
0b3859521a arch: fix the sched parameter update when exiting 
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
 2024-10-08 13:53:06 +08:00
xuxingliang
33a8760a14 arch/sim: fix uart could lose log 
Need to loop to write untill all data written or error happened

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
 2024-10-08 08:57:28 +08:00
Xiang Xiao
904bb7a6ea arch/sim: dataheap should disable exec permission 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2024-10-08 08:57:28 +08:00
yinshengkai
bdcc325e1f sim/gcov: Fix conflicts between fprofile-orderate and __asan_default_options 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-08 08:57:28 +08:00
yinshengkai
acca2430a9 Revert "arch/sim: suppress libasan checks" 
This reverts commit 53ddc3ef7f

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 08:57:28 +08:00
ligd
a3568af105 sim: fix context-switch when do wdog callback() 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 08:57:28 +08:00
ligd
ba3a55b445 cache: do cache_invalidate_all before enable dcache 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-08 08:15:41 +08:00