Per further feedback from Litex community, the vexriscv cache is
write-through so no flush is required - therefore, make it a nop.
And add a pointer to vexriscv invalidation magic instr docs.
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
The riscv_vpuconfig() was defined but never called in qemu_rv_start. This caused mstatus.VS to remain disabled, leading to Illegal Instruction exceptions when the OS attempted to use vector registers. This patch adds the missing initialization call.
Signed-off-by: ENJOU1224 <enjou1224@outlook.com>
The riscv_savevpu/restorevpu functions were using 'uintptr_t *' for vector registers, but 'tcb->xcp.vregs' is defined as 'uintreg_t *'. This mismatch caused compilation errors on GCC 13+ due to incompatible pointer types. This patch aligns the parameter types to 'uintreg_t *'.
Signed-off-by: ENJOU1224 <enjou1224@outlook.com>
Most of the peripheral support matches litex vexriscv-smp.
* arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64.
* arch/risc-v/src/litex/Make.defs
arch/risc-v/src/litex/hardware/litex_clint.h
arch/risc-v/src/litex/hardware/litex_memorymap.h
arch/risc-v/src/litex/hardware/litex_plic.h
arch/risc-v/src/litex/litex_irq.c
arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV
conditional where vexriscv_smp conditionals are.
* boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config.
* boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion.
* boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map.
* boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for
toolchain happiness matching other RISC-V linker scripts.
(This commit was written with assistance from Claude Code.)
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
This duplicates the up_invalidate_dcache_all as vexriscv's DBUS cache
does not distinguish between flushing and invalidation.
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
Previously only up to 31 PIO instructions were accepted.
But the hardware allowed 32 instructions.
Now we accept 32 instructions.
See the corresponding commit in the pico-sdk repository:
6f7dc67791
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
Upperhalf supports multiple working modes at the same time,
which is specified by NIC when register
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Modifies Kconfig and build tools to support flash encryption
and E-Fuse burning when flash encryption is enabled.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
- ARCH_CHIP_ESP32C3_LEGACY created
- ARCH_CHIP_ESP32C3_GENERIC is now ARCH_CHIP_ESP32C3
This is part of deprecating esp32c3-devkit as esp32c3-legacy and
using esp32c3-generic (now esp32c3-devkit) instead.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Update the CA training result check to match the HSS reference code.
The original check which required phase delays to be 5 taps separated was wrong.
This has also been removed from the HSS.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
The window is 32 taps, so in order to the eye to be completely inside the window,
the (offset + width) has to be less or equal than (32 - margin).
Add this additional sanity check in the mpfs_training_verify.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Since the bl602 do not support the atomic extention, we should compile
it with `-march=rv32imfc`, or it will fail to boot when executing the
`lr.w` instruction.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
Directly downloading the Git repository is inconvenient for local debugging.
This will allow to automatically download external packages from the Internet.
If not set, the repo need to be download will need to provide them manually,
otherwise an error will occur and the build will be aborted.
Add `USE_NXTMPDIR_ESP_REPO_DIRECTLY`, with this we can use
`USE_NXTMPDIR_ESP_REPO_DIRECTLY=y make` which can directly use esp-hal-3rdparty
under nxtmpdir without CLONE, CHECK_COMMITSHA, reset, checkout and update. Just
`cp -rf nxtmpdir/esp-hal-3rdparty chip/$(ESP_HAL_3RDPARTY_REPO)`.
Signed-off-by: v-tangmeng <v-tangmeng@xiaomi.com>
In MSS CAN transmit function, the check of net pkt data len is not neccessary. Since there are cases that the pkt len can exceed the expected 16 bytes of can_frame but the pkt is still valid. Such a case is when CONFIG_NET_CAN_RAW_TX_DEADLINE is enabled which has pkt len to become 32 bytes due to cmsghdr overhead.
Signed-off-by: haitomatic <hai.to@unikie.com>
The Nuttx MSS CAN driver has an exclusive interface to the integrated MSS CAN peripheral residing in Polarfire SoC FPGAs. There are two CAN block 0 and 1 that can be configured for use. In normal mode (non AMP), CAN0 and CAN1 block base register addresses are 0x2010C000UL and 0x2010D000UL.
Signed-off-by: Hai To <hai.to@tii.ae>
Updates the SPI Flash driver used for user storage MTD.
Updates board linker script and bring up.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The nxsched_switch_context() function should only be called
when a task switch actually occurs. The RISC-V architecture
already performs this call in riscv_perform_syscall(),
so this PR removed the redundant nxsched_switch_context() call in
up_switch_context().
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Updates the common source code for the SPI peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit refactors the I2S common driver for Espressif's RISC-V
SoCs. Previously, the peripheral was not working as expected.
Along with the new I2S character driver, this new I2S lower-half
driver can be easily tested using internal loopback between the
transmitter and receiver channels.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
