Add an option to use HPWORK queue for ethernet driver, to reduce
delays if more time critical messaging via ethernet is wanted.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add a function imx9_lpspi_select_cs to assert CS at the start of
an SPI transfer and keep it asserted until called again to
de-assert it. This can be called by board-provided imx9_lpspi_select,
in case the CS needs to be controlled via the LPSPI block and not
GPIO.
The TCR register CONT (continue) bit is asserted to prevent CS toggling
during the transfer, and the PCS bits are set to mark the correct CS
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
According to the TRM, only bits 24-25 are reserved for chip select, and
the maximum number of internal chip selects is 3 (on LPSPI4 bus only).
Fix the TCR_PCS_MASK and remove extra definitions.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit aligned the arm64 generic timer count to the tick boundary. Notice that this is just a work-around. We should pass both the current system ticks and the delay ticks as input parameters. But we only have the delay tick here due to the oneshot interfaces.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
1. up_irq_save should not mask fiq if CONFIG_ARCH_HIPRI_INTERRUPT=y
2. up_irq_save should mask fiq if CONFIG_ARCH_TRUSTZONE_SECURE=y
3. up_irq_save should mask irq if CONFIG_ARCH_TRUSTZONE_SECURE=n
4. add up_secure_irq in arm64
5. add ARCH_HAVE_TRUSTZONE support for ARCH_CORTEX_R82
Signed-off-by: hujun5 <hujun5@xiaomi.com>
MTDIOC_RESET ioctl command executes "Reset Enable" and "Reset Memory"
commands to enter a power-on reset condition.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Introduces a very basic frame buffer driver implementation for the RPi4B
which is registered at startup and works with frame buffer graphics
examples (and LVGL). Graphics are displayed on the HDMI0 and HDMI1
output, depending which one is plugged into the display. I have not
tested using both at once, nor does the driver account for that. They
are both referred to as display 0, plane 0 since the RPi4B frame buffer
interface does not seem to have a way of distinguishing.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Gdbstub demo::
The Qemu version must be above 9.2 to support two serial ports.
One window:
./tools/configure.sh qemu-armv8a:gdbstub; make -j25
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -kernel ./nuttx -serial mon:stdio -serial pty
char device redirected to /dev/pts/27 (label serial1)
- Ready to Boot Primary CPU
- Boot from EL2
- Boot from EL1
- Boot to C runtime for OS Initialize
Another window:
gdb-multiarch nuttx -ex "target remot /dev/pts/27"
GNU gdb (Ubuntu 15.0.50.20240403-0ubuntu1) 15.0.50.20240403-git
Copyright (C) 2024 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from nuttx...
Remote debugging using /dev/pts/26
gdb_get_registers (state=0x403e1590) at gdbstub/lib_gdbstub.c:1020
1020 reg = state->running_regs;
(gdb) c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Replace the spinlock/sched_lock pair in arm64/imx9 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
This initial implementation sets up support for the EMMC interfaces on
the BCM2711. Only EMMC2 is tested since it is the interface of interest
(connects to uSD card). MMCSD communication is functional and the boot
partition of the SD card can be mounted and interacted with.
Insertion/removal interrupts do not fire after initial boot, and
sdstress fails with any byte size larger than 1023. 32GB card works
perfectly, while 64GB card exhibits strange behaviour when interacting
with VFAT filesystem.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
Add simple single ID mask filter. Only pkts with set CAN ID are accepted. This works for both STD and EXT CAN ID.
Signed-off-by: haitomatic <hai.to@unikie.com>
Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
After irq_dispatch finished, the interrupt stack will be checked to
determine whether overflow occurs.
The relevant configuration reuses the configuration of stack overflow
detection during context switching.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
A basic implementation of mailbox API with some helpers for accessing
properties implemented. Uses busy-wait due to documentation challenges
with mailbox API.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Many times, context switching does not occur when the thread stack
memory is almost exhausted, so we need to mofify up_check_tcbstack to
accurately detect it.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
The arm-m architecture svc call will trigger an interrupt,
and the actual context switch is executed after doirq is completed,
so only the scheduling information needs to be updated in doirq.
In the arm-a/r architecture, interrupts and syscalls are independent,
and scheduling information needs to be updated in both locations
Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
The interrupt handler accesses the device as well as the driver's private
data. Use critical_section for mutual exclusion with drivers/usbdev, which
also protects the same data with critical_section.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
These archs only align the size of the stack, forgeting to do the
stack start addr alignment, this patch fixes it.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Initial I2C implementation such that I2C sending and receiving now
works well enough to use the BMP280 driver for a BMP280 device connected
to any of I2C0-I2C6 on the default pins. I2CTOOL also works for these
interfaces.
Functionality for "no stop" and "no start" options is not present.
Implementing that is not clear from the peripheral datasheet and will be
a challenge.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
imx9_lpi2c_reset didn't quite work. It tried to toggle scl line as GPIO, but the line was not even muxed properly.
Instead, set the bus to relaxed mode, and drive address 0 to the bus. This toggles the clock, and also generates start and stop sequences on the bus.
"Relaxed mode" is a new feature on the LPI2C block used in imx93.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- In case of warm reboot, clear active and pending interrupts from GICv3
and also from the CPU interface.
- Fix default IGROUPMODR to the reset value (0)
- Move gic_wait_rwp calls to after modifying ICENABLER
- Improve some comments
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
When delivering a signal to a kernel task, or in CONFIG_BUILD_FLAT with MMU
enabled, the REG_SCTLR_EL1 needs to be stored for exception return.
Otherwise 0 is restored to the register at exception return, MMU is switched off
and the system crashes.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This fixes the same issue for other targets, which was already fixed for
xtensa in commit 50d94863.
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[xx]) will enable them if they were
enabled in the context.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Align the writing style of arm cmake, and each compiler defines its own find library
function, otherwise use the default
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The tx int handler will call uart_xmitchars() to make a fake interrupt event,
but this is unsafe after enabling interrupts. This PR will add a critical section
to ensure that the txint process will not be interrupted by the IRQ
Signed-off-by: chao an <anchao.archer@bytedance.com>
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
