On the linum-stm32h753bi, Ethernet throughput collapses in proportion to
what the display panel is showing. With the LTDC scanning a black screen
a 1.2 MiB TCP transfer to a wired peer takes 0.7 s; solid white takes 20
to 55 s and noise over 130 s, all at the same negotiated 100BASE-TX full
duplex, with the same bytes read from the same SDRAM. The display's
switching couples into the PHY hard enough to corrupt 100BASE-TX
signalling, and TCP grinds through the losses at whatever rate survives.
10BASE-T signals at 2.5 V with Manchester coding at a tenth of the
frequency, and does not care: black, white and noise all move at the
link rate. The same transfer that took five minutes with the display
rendering takes 5.6 seconds.
Restricting the ANAR advertisement is deliberately not the same as
disabling autonegotiation. A forced MCR leaves the partner to parallel
detection, which cannot sense duplex and picks half, a genuine
mismatch, verified here to stall bulk traffic completely. Advertising
only 10BASE-T full duplex keeps the negotiation and lands both ends on
the same mode.
Also fix the never-compiled !CONFIG_STM32_AUTONEG path, which still
called stm32_phywrite(); this driver has only ever had mdio_write().
And say what was negotiated at link-up: a duplex mismatch looks exactly
like a bad cable, and nothing else reports which of the two it is.
The vnc configuration of the linum board enables the new option, and its
packet pool sizing from a few commits ago stays: at any link speed, 24
buffers of 196 bytes was never going to stream a display.
Assisted-by: Claude:opus-5
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
The check added by the preceding commit reports ten braces in nxstyle.c
that do not line up with the brace they close, and a comment that does
not share the column of the run it belongs to. Bring the whole file
into line with the standard, so that the checks added by the commits
that follow are not introduced against a file that breaks them.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Braces were only tested against a multiple of the indentation unit, so
one at the wrong level still passed.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add CRC header based on arch/arm/src/common/stm32/hardware/stm32_crc.h
and select STM32_HAVE_CRC in Kconfig
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Posix open() calls to /dev/adc# were hanging often due
to the ready loop check at the end of adc_enable() never
returning. According to ES0565 document, at least 4 ADC
clock cycles must pass between the time we waited for
calibration to end and before we can set ADEN. This will
depend on what clock is set for ADC. So to ensure enough
time passes, we are adding a short delay (so that even a
slow clock will work). Also, we are clearing the ADRDY
flag before hand to ensure we are detecting a fresh event.
The delay to wait for the voltage regulator is also
increased to account for extra time required in
non-ideal conditions.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
The 20 selects that were repeated identically in every STM32_STM32H7*
helper are moved to STM32_H7_PERIPHERALS, leaving only the chip
specific ones in the per-family helpers.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add a driver for the STM32H7R/S XSPI controller. The driver implements
the NuttX QSPI interface and supports the memory-mapped mode used to
execute code from the external flash.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
Move the STM32U5 startup, interrupt, GPIO, EXTI, serial, heap, idle, and
timer interrupt implementations into arch/arm/src/common/stm32.
This prepares the Cortex-M33 support for reuse by compatible STM32 families.
Assisted-by: OpenAI Codex:gpt-5
Signed-off-by: raiden00pl <raiden00@railab.me>
Recognize variable-length ANSI SGR sequences and consume
them without changing attributes so unsupported color
controls are not rendered as terminal text.
Signed-off-by: raiden00pl <raiden00@railab.me>
Handle carriage return, cursor-left/right, and erase-to-end-of-line
sequences required by readline. Restore glyphs hidden by the cursor
so edited text redraws correctly.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
Treat PCI_ANY_ID in a configured UART slot as a wildcard while
still limiting probes to devices supported by the PCI 16550 driver.
This lets one console configuration select QEMU PCI serial or
the real PCI card at runtime.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
Document the USART2 NSH console, USB FS pins, HSI48/CRS clock source and
the usb-cdc configuration that exposes a separate USB CDC/ACM serial
device.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The STM32L073RZ provides a full speed USB device controller, but the
Nucleo-L073RZ board support did not enable it and no configuration
exercised it.
Add the pieces required to run USB device mode on this board:
- Add the USB device pin definitions to the STM32L0 pin map.
- Provide board level pull-up control using the embedded DP pull-up in
USB_BCDR, and register the CDC/ACM class at boot when it is selected.
- Add a usb-cdc configuration that presents an NSH console on USART2 and
a CDC/ACM serial device on USB.
The 48MHz clock for the controller is supplied by HSI48 trimmed from the
USB start of frame packet, which is the crystal-less USB configuration
already described by this board's board.h.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Adds reference to the sdmmc_spi defconfig of esp32p4-tab5, with mounting
instructions for the SD Card.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Adds support for using SD Card on esp32p4-tab5 board.
Common source is added to esp32p4 common board directory which can be used
on different boards.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Return unsupported-format and mapping errors to board bring-up
instead of panicking, so a serial console can remain usable when
no suitable framebuffer exists.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
x86_64_uservaddr() depends on the address-environment layout and
is only consumed by the kernel address-environment path.
Guard it with CONFIG_ARCH_ADDRENV so MM_PGALLOC can also be
enabled in flat builds.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
read_line() removes a trailing newline and then checks g_line[len - 1]
for a line-continuation backslash. A blank line leaves len at zero, so
the continuation check reads before g_line.
Return the empty line to the caller before checking for a continuation.
kconfig_line() already skips empty lines, so parser behavior is
unchanged.
Signed-off-by: Old-Ding <ai.neo.ae86@gmail.com>
Python warns about return statements inside finally blocks because they
can suppress pending exceptions. Move the returns after the try/finally
and try/except bodies so normal return values stay the same while
unexpected exceptions are no longer swallowed.
Signed-off-by: Old-Ding <ai.neo.ae86@gmail.com>
Python 3.14 warns about invalid escape sequences in a few tooling strings. Escape those backslashes at the Python literal layer; the licensing regex AST stays unchanged, and the IDE exporter change only corrects the docstring path example.
Run black on tools/licensing/check.py so the licensing helper matches the project formatting check.
Signed-off-by: Old-Ding <ai.neo.ae86@gmail.com>
status() reads one reset line at a time, and only for a caller that
already knows the id. Nothing else in the interface says how many lines
a controller has or what any of them resets, so the lines a board is
holding cannot be surveyed.
Adds an optional get_line method describing one line as a structure: its
name, and a text member for controller specific fields the structure
does not cover. The asserted state stays with status(), which already
reports it, so a controller does not supply the same fact twice.
Returning -ENODEV reports an id that names no line, which is how
controllers with gaps in their numbering are handled.
reset_controller_dev gains the line count that bounds the ids.
CONFIG_RESET_PROCFS adds /proc/reset, one key:value line per reset line,
every line the same tokens in the same order so the file is machine
parseable. A controller without get_line is listed by name and a note.
The controller list already existed for reset_control_get() to search,
so the renderer only walks what was there. /proc/reset is claimed when
the first controller registers; procfs_register() requires that procfs
is not yet mounted, which holds because controllers register during
board or architecture start up, and it appends without checking for
duplicates, so the entry is claimed once for the lifetime of the system.
Documents the framework, which had a page with nothing on it: the
consumer interface and what shared and exclusive handles mean, the
controller interface, the new method, and /proc/reset.
Off by default and costs nothing when off. No in-tree configuration
enables RESET, so this builds only when a board turns it on.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The pinctrl interface is write only: every operation sets a property,
and nothing reports what a pin currently holds.
Adds an optional get_pad method describing one pad as a structure: the
settable fields, each with a validity bit because a pad need not have
them all, and a text member for the controller specific fields the
structure does not cover. The structure embeds its strings rather than
pointing at them, so the same shape serves both callers.
The first caller is /proc/pinctrl, which renders one key:value line per
pad, every line the same tokens in the same order with - for a field the
pad does not have, so the file is machine parseable. The framework owns
the format; controllers only supply data.
The second is a new PINCTRLC_GETPAD ioctl, which gives userspace the
read-back that text cannot: reading a pad back after setting it.
PINCTRL_PADNAME() and two lookup helpers let a controller declare its
pad and function-select names in one table instead of inventing its own.
Registration keeps a list, which the renderer iterates; pinctrl_dev_s
gains the pad count. /proc/pinctrl is claimed when the first controller
appears; procfs_register() requires that procfs is not yet mounted,
which holds because controllers register during board or architecture
start up.
Documents the method, the validity bits and the optional naming, and
records that /proc/pinctrl exists.
Off by default and costs nothing when off. No in-tree configuration
enables PINCTRL, so this builds only when a board turns it on.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The stm32h5 SPI driver had some issues when both
non-DMA and DMA instances were present at the same time.
Modify the driver to allow them to correctly coexist.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
The stm32h5 SPI driver is based on stm32h7's.
It does not build when DMA is enabled. Port
stm32h5 DMA to the stm32h5 SPI driver using the
H5-specific DMA API. Use equivalents.
Use correct cache line definition.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Add board spi1 initialization and generic spi
chardev registration for nucleo-h563zi.
Specify the SPI1 clock source and frequency on
this board for the spi driver.
Define the SPI pins for this board. The SPI_A
CN7 header pins were used.
Include stm32_spi.h in stm32h5/stm32.h.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
The standard requires braces after 'if', 'else', 'while', 'for' and 'do'
even when the body is a single statement. Nothing checked this.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Decode the saved setup request fields after processing the optional OUT data phase. This ensures the fields are initialized when the EP0 handler is entered again to complete an OUT control transfer.
This also fixes Clang builds that treat the resulting maybe-uninitialized diagnostics as errors.
Assisted-by: Codex:GPT-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Add the correct pin map definitions for MCO1 and MCO2, and add the clock
division option to stm32_mco{1,2}config with a macro. This matches the
STM32H7 implementation.
Signed-off-by: Darryl Ring <darryl@bluerobotics.com>
Update the MIPS Creator CI20 board documentation to include a detailed
peripherals support table. This replaces the basic bulleted list with
comprehensive status details for CPU cores, RAM, Display, Ethernet,
GPIO, TRNG, Timers, UART0, USB Host, and Watchdog.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
romfs_seek() clamps the computed position to the file size when it
exceeds rf_size, but never checks for a negative result. lseek(fd,
offset, SEEK_SET/SEEK_CUR/SEEK_END) with an offset that produces a
negative position (e.g. a negative SEEK_SET offset, or a SEEK_CUR/
SEEK_END offset more negative than the current position/file size)
is written straight into filep->f_pos.
The subsequent romfs_read() computes
`rf->rf_startoffset + filep->f_pos` into a uint32_t, so a negative
f_pos wraps around to a huge unsigned offset, and romfs_hwread()'s
XIP path memcpy()s from rm_xipbase plus that offset -- an
out-of-bounds read far past the mapped flash region.
Add the same "if (position < 0) return -EINVAL" guard already used
by fs/fat/fs_fat32.c's seek function, before the existing
end-of-file clamp.
Signed-off-by: yi chen <94xhn1@gmail.com>
Assisted-by: Claude:claude-sonnet-5
Fix NULL pointer dereference and memory corruption by using
file_put() instead of file_close() + kmm_free().
Add peer NULL check to local_freectl().
Signed-off-by: Bogdan <Bogdan4ik0759@gmail.com>
Document the usb-cdc-uart configuration, which keeps NSH on the USART2
ST-LINK virtual COM port and exposes a separate USB CDC/ACM serial
device on the STM32 USB FS connector.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The STM32F072RB provides a full speed USB device controller, but the
Nucleo-F072RB board support did not enable it and no configuration
exercised it.
Add the pieces required to run USB device mode on this board:
- Select HSI48 as the 48MHz source and use the USB start of frame packet
as the CRS synchronisation event, which is the intended crystal-less
USB configuration for this part.
- Add the USB device pin definitions to the STM32F07x pin map.
- Provide board level pull-up control and register the CDC/ACM class at
boot when it is selected.
- Add a usb-cdc-uart configuration that presents an NSH console on
USART2 and a CDC/ACM serial device on USB.
- Enable the USB device pins in the nsh configuration so the two
configurations stay consistent.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
clock_gettime(CLOCK_MONOTONIC) reads g_system_ticks, which is only
refreshed when a timer expiration is processed. On SCHED_TICKLESS an
idle system has no timeout armed, so the clock returns 0 before the
first expiration and a frozen value afterwards.
This regressed in commit c7b6442974, which switched CLOCK_MONOTONIC to
the sched tick counter to exclude suspended time. Excluding suspend time
needs explicit accounting maintained by PM code, the tick counter cannot
provide it on tickless.
Restore the live read. On non-tickless builds clock_systime_timespec()
falls back to the same tick counter, so behavior there is unchanged.
Verified on qemu-intel64, nrf52840-dk and rv-virt.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
vrefint_enable() sets SYSCFG_CFGR3_ENBUFVREFINTHSI48 in its local copy
of the register value but never writes that value back to the hardware.
The VREFINT reference for the HSI48 scaler is therefore never enabled.
Only the earlier ENVREFINT update reaches the register, so VREFINT
itself is enabled while the HSI48 reference is not. HSI48 then runs
without its voltage reference and the 48MHz clock is not accurate enough
to be used by the USB device controller.
Write the register after applying the HSI48 reference bit.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
STM32_HSI48_SYNCSRC was SYNCSRC_NONE, which makes stm32_enable_hsi48()
return before configuring the CRS at all. HSI48 then free runs at its
untrimmed factory frequency, which is not accurate enough for USB full
speed operation.
The board has no CRS_SYNC pin wired and does not fit an LSE crystal for
this purpose, so the USB start of frame packet is the available
synchronisation source. This is the intended configuration for
crystal-less USB on this part.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
