Curently, the driver code for HW accelerated AES is not usable
since it's not registered within esp32_crypto. This commit fixes
it as well as a few bugs.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
Fix exception issue when PM and DEBUG_ASSERTIONS enabled for esp32 and esp32s3.
This error happens due to PM system workflow, when system gets into sleep-modes with
removing PM_NORMAL count, system is raising an exception for not having
enough number of PM_NORMAL state count if DEBUG_ASSERTIONS enabled.
Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
When closing a serial port an ongoing TX DMA transfer will be stopped. This can cause
one (or multiple) the following:
- dev->dmatx.length != 0
- dev->dmatx.nlength != 0
- stm32_dmaresidual returning a non-zero residual
This is caused by length/nlength not being set to 0 at startup or during closing.
In addition the DMA_SxNDTR register is not set to 0 at startup or during closing.
This commit solves the issue by setting the variables and register to 0 during closing.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
arch/arm/stm32h7: Add review feedback regarding style
Removed non-needed spaces.
Aligned style of documentation.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
The nxsched_switch_context() function should only be called
when a task switch actually occurs. The RISC-V architecture
already performs this call in riscv_perform_syscall(),
so this PR removed the redundant nxsched_switch_context() call in
up_switch_context().
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Updates the common source code for the SPI peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit refactors the I2S common driver for Espressif's RISC-V
SoCs. Previously, the peripheral was not working as expected.
Along with the new I2S character driver, this new I2S lower-half
driver can be easily tested using internal loopback between the
transmitter and receiver channels.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Adds Kconfig knobs for the ESP32-S3 RX FIFO full threshold and timeout and wires them into the UART driver.
Clears RX FIFO overflow interrupts by resetting the hardware FIFO so reception resumes cleanly.
Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
Add simple single ID mask filter. Only pkts with set CAN ID are accepted. This works for both STD and EXT CAN ID.
Signed-off-by: haitomatic <hai.to@unikie.com>
When SEMIHOST_SYSLOG is enabled it creates its own up_putc() function
however the stm32_serial.c also creates this same function, even
when all STM32_USARTs are disabled. Fix patch fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Updates MCUBoot version and default address for virtual E-Fuse, depending
if MCUBoot is enabled.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
The current implementation does not call
nxsched_switch_context() exactly when a
task switch occurs.
This patch fixes the issue by placing the
call at the correct location.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Remove the comment which is copy-paste from stm32/stm32_eth.c.
stm3240g-eval doesn't contain any valuable information about eth driver.
If we need to find an explanation of the configuration options, they are in
Kconfig files.
Signed-off-by: raiden00pl <raiden00@railab.me>
clock_systime_timespec() always returns 0, so there is no need to
check the return value in the caller code, let us remove the return
value directly.
Signed-off-by: chao an <anchao.archer@bytedance.com>
E51 needs to use vendor specific CSR to enable L1 cache.
This adds the relevant register setting and makes it
configurable by CONFIG_MPFS_E51_ENABLE_CACHE. With this flag set, the L2
cache on E51 depends on the cache lane configuration. Disabling this flag
disables all caches on E51.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This adds a header file, defining microchip's vendor specific
CSR registers for E51 monitor core on MPFS SoC
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Incorrect FSM status checks in the suspend path could cause
deadlocks when power management was enabled. This patch fixes
the condition to allow proper UART suspend/resume handling.
Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
Updates the common source code for the LEDC peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Add FLASH support for STM32C0 based on STM32G0 FLASH driver.
FLASH support is identical for these two, except that the STM32G0 can support
dual bank, which is not available in the STM32C0.
Signed-off-by: raiden00pl <raiden00@railab.me>
Updates the common source code for the SHA accelerator used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
PWR is not supported for STM32C0 yet, fix build error when CONFIG_STM32F0L0G0_PWR=y
which is required to access backup registers (we need enable PWR clock for this).
Signed-off-by: raiden00pl <raiden00@railab.me>
Updates the common source code for the GPIO peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
update STM32C0 PWR registers:
- there is no F,G,H and I GPIOs, so we can remove some registers
- add definitions for PWR backup registers
Signed-off-by: raiden00pl <raiden00@railab.me>
Updates the common source code for the PCNT peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the MCPWM peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Fix tricore running issue introduced by PR17060.
The bug is that when irq returns, the running_task was not
updated to the current task with highest priority from
the scheduler readytorun_list
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
