The parameter count of read had to be a multiple of 4, otherwise the
result was truncated. Now all values are possible.
Signed-off-by: Mathias Duckeck <mathias.duckeck@avat.de>
- Fix EtherCAT signals drive strengh (from errata PORTS_CM.H002), caused bus faults.
- Changed xmc4_ecat.c for compile time pin definition.
- Fixed xmc4_ecat.c register not written (reset value already used).
- Removed EXTCLK for xmc4800 as pin is used for ECAT.
- Clean xmc4 familly board.h and clocks config.
Signed-off-by: adriendesp <adrien.desproges@gmail.com>
This commit adds support for SPI_SETDELAY operation on SAMv7 QSPI
peripheral running in SPI mode. The logic is the same as for standard
SPI peripheral, just different registers. The change allows to set
custom delays between transfers, chip selects and so on.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
During I2C read, one-too-many byte is read, which can lead to the I2C bus
getting stuck. This is likely due to the STOP condition being set at the
wrong time or being missed completely. The chip offers a shortcut, such
that the STOP condition is set automatically after the last byte is being
written/read.
Signed-off-by: Max Kriegleder <max.kriegleder@gmail.com>
When TICKLESS not enabled, up_alarm_set_lowerhalf will call start, if we
overwrite the compare register will cause TICK mode no longer isr.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
In multi-core environment where NuttX runs on each core, if one core
sets the RTC time, the RTC value gotten on other cores is incorrect.
This is caused by clock_gettime(CLOCK_MONOTONIC) function used to get
elapsed time, which uses a core-specific global varaiable g_basetime
as the base time.
To fix this, update the g_basetime from the backup SRAM that can be
shared between cores in setting/getting the RTC time.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
- Added PWM driver support for the RA4M1 microcontroller using the GPT timer.
- This driver supports Saw-wave mode and one of the two output channels (A or B).
- Added necessary configurations in CMakeLists.txt, Kconfig, and Make.defs.
- Created new header file for GPT.
Signed-off-by: leocafonso <leocafonso@gmail.com>
Use clock_get_sched_tclock_systime_ticks() to access system ticks
in order to fix the build error and improve code safety.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
The .align N syntax in GHS means the alignment is N Bytes. In GCC
compiler, it means 2**N Bytes. Therefore, .align 32 in GHS and
.align 5 in GCC are equivalent.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
The $+0x0 is not accepted by Ghs compiler. Therefore, we change it to a
more common syntax " b ." for endless self loop.
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
The GreenHills Compiler uses Unified Assembler Language by default and
it does not recognize .syntax unified instruction. Therefore, remove
them if GHS compiler is used.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
The GreenHills Compiler uses different grammer for the .type directive
in asm, this patch adds support for the grammer for arm-v8r.
Similar change for arm-v7r was done in pull request #12883.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
Fix a transfer issue in the Kinetis DSPI driver when operating
with transmit and receive FIFOs disabled (`MCR[DIS_TXF]=1`,
`MCR[DIS_RXF]=1`). In this mode, the DSPI module behaves as a
simple double-buffered SPI interface without TX staging.
When FIFOs are disabled, `PUSHR` acts as a single 32-bit
command/data register. Partial (16-bit) writes to its upper or
lower halves can result in incomplete or corrupted transfers.
This patch ensures the full 32-bit packet is prepared and
written in a single operation.
* Resolves broken SPI transactions with LAN9252 (EasyCAT).
* Improves reliability in non-FIFO DSPI configurations.
* No impact on DMA or FIFO-enabled modes.
Signed-off-by: trns1997 <trns1997@gmail.com>
Replace the spinlock/sched_lock pair in arm/stm32 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/sam34 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/s32k3xx with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/s32k1xx with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/kinetis with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/imx9 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
By default, the full configured DTCM region is assigned to the heap for
dynamic allocation. In scenarios requiring deterministic memory regions
for static buffers or control structures, you can reduce the heap
allocation to reserve part of DTCM for manual/static use.
This kconfig symbol allows to limit the size.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The adc_dmaconvcallback routine was far too slow and inefficient. This was not caught until recently when I was testing faster sample rates. When in circular mode for the adc (dma and constant conversions), the adc_dmaconvcallback function would overwhelm the OS and lock it up. I looked into this and did a lot of testing. First I tried minimally improving the dma callback by removing the % operator from the algorithm, this was slow and inefficient. I also tried increasing the batch size considerably as well as the fifo size. This helped but the OS would still lockup with the fastest sample rate (5 Msps). au_receive_batch was the solution. In order to use this, I needed to change the dmabuffer to be of type uint32_t to match the data pointer in au_receive_batch. I also needed to create a channel buffer, which is initialized once in adc_setup. stm32_gpdma_cfg_s->tr1 needed to be updated for the uint32_t dmabuffer. Once I made changes to use au_receive_batch, I could reliably use the fastest sample rate without locking up the OS. Calling au_receive for every single conversion in a batch is far less efficient than calling au_receive_batch. I also snuck in some changes for the ADC watchdog defines and guards. These were fixes that were tested while testing these changes.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
This function can identify (during the runtime) whether the chip
is revB or revA. Bear in mind PIC32CZ2051CA70 is always revB.
Allows to have one binary compatible with SAMV7 and PIC32.
Thanks to Pavel Pisa and Michal Lenc for the suggested code.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
Previously the function "up_cpu_pause" was used for preventing all other
CPUs from executing code from flash.
The above function was removed in d8cb7759.
Now flash operations work on rp2040 in SMP mode by blocking all but the
current CPU for the duration of the critical function (write or erase).
Closes: #16203
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
Adding the stm32h5 pwm driver. This is almost an exact copy of the stm32h7 pwm driver. I confirmed the timers for the h5 are version v2 and added the preprocessor definition. This commit was tested on a stm32h5 nucleo-h563zi development board. Necessary board files and a pwm config have been added. Added pin mappings for all timer outputs.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
Added documentation regarding nucleo-h563zi:pwm config.
Removed CONFIG_STM32H5_PWM guard at the top. Fixed IRQs for tim1 and tim8. Added H5 to list of Timer IP v2 timers.
Conditionally compile stm32_serial.c.
Add stm32_pwm.c to CMakeLists.txt
When closing a serial port an ongoing TX DMA transfer will be stopped. This can cause
one (or multiple) the following:
- dev->dmatx.length != 0
- dev->dmatx.nlength != 0
- stm32_dmaresidual returning a non-zero residual
This is caused by length/nlength not being set to 0 at startup or during closing.
In addition the DMA_SxNDTR register is not set to 0 at startup or during closing.
This commit solves the issue by setting the variables and register to 0 during closing.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
arch/arm/stm32h7: Add review feedback regarding style
Removed non-needed spaces.
Aligned style of documentation.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
When SEMIHOST_SYSLOG is enabled it creates its own up_putc() function
however the stm32_serial.c also creates this same function, even
when all STM32_USARTs are disabled. Fix patch fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
