Add a Peripheral Support section to the board page listing the GPIO and
MCU_MCSPI0 drivers, and replace the "UART console only" warning on both
the chip and board pages -- it no longer describes the port. The
replacement states what actually constrains the port: NuttX runs on the
R5F under RemoteProc and depends on the bootloader or Linux Device
Manager having powered and clocked the peripherals, because there is no
TISCI client yet.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds the AM67 GPIO lower half and a polled MCU_MCSPI0 master driver, with the
pad configuration both need. The K3 instance is not the OMAP2 layout: an HL
header block precedes the functional registers.
Chip select is released only after CHSTAT.EOT, since a high SCLK otherwise
drops it mid-word and truncates the write, and CHCTRL.EN stays asserted between
transfers.
t3-gem-o1 registers /dev/spi0 for its ICM-20948 (CS3) and LPS22DF (CS1), and
raises NSH_MAXARGUMENTS to 16 so the spi tool can address a device.
Verified on t3-gem-o1: WHO_AM_I reads 0xEA on CS3 and 0xB4 on CS1, and the
ICM-20948 streams continuous accelerometer samples over the bus.
Co-authored-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Assisted-by: Cursor
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Follow-up to the previous commit, which switched every flat-build
rv-virt nsh defconfig from nsh_main to nxinit (init_main) but left
pnsh and pnsh64 (CONFIG_BUILD_PROTECTED=y) on nsh_main. Under protected
build nxinit's "console sh" service failed to start:
posix_spawnp("sh") resolves through the kernel-space binfmt "builtin"
loader / BINFS, but the kernel-space g_builtins/g_builtin_count table
those rely on was never populated -- CONFIG_BUILD_PROTECTED links
apps/builtin/builtin_list.c only into the user blob (nuttx_user), and
nothing called the boardctl(BOARDIOC_BUILTINS) hand-off NuttX has
provided for this since release 8.1.
With that hand-off now issued by apps/system/nxinit early in init_main()
(nuttx-apps, "system/nxinit: register g_builtins with the kernel under
PROTECTED build"), pnsh/pnsh64 can use nxinit like every other
flat-build rv-virt nsh defconfig. Apply the same minimal
nxinit-essential delta used for the 23 configs switched previously.
Verified on rv-virt:pnsh: `ps` shows init_main as the parent with sh
as its Running child, `ls /bin` lists the builtins, and `hello` runs
(see the PR description for logs).
Assisted-by: opencode-agent/claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Switch every rv-virt (qemu-rv) flat-build defconfig whose init entry
point was nsh_main to nxinit (init_main): citest, citest64, fb, fb64,
flats, flats64, leds, leds64, leds64_rust, leds64_zig, libcxx,
libcxx64, lvgl64_vector, netnsh, netnsh64, netnsh64_smp, netnsh_smp,
nsh, nsh64, python, smp, smp64, virt_nsh (23 configs; pnsh/pnsh64 are
switched in the following commit). nsh now runs as a "console sh"
service started by init.rc instead of being the top-level init task,
matching boards/arm/qemu-armv7a, boards/arm64/qemu-armv8a and
boards/sim. elf (elf_main) and the 11 kernel-build configs (which use
CONFIG_INIT_FILEPATH) are out of scope and untouched.
Each switched defconfig gains only the nxinit-essential keys
(regenerated with make savedefconfig): CONFIG_INIT_ENTRYPOINT="init_main",
CONFIG_SYSTEM_NXINIT=y and its deps (CONFIG_EXPERIMENTAL,
CONFIG_LIBC_EXECFUNCS, CONFIG_SCHED_CHILD_STATUS), and
CONFIG_ETC_ROMFS=y/CONFIG_FS_ROMFS=y to ship init.rc via ROMFS.
Add boards/risc-v/qemu-rv/rv-virt/src/etc/init.d/init.rc registering a
"console sh" service (guarded by CONFIG_SYSTEM_NSH), shipped via ROMFS
in both the Make (RCSRCS, only when CONFIG_ETC_ROMFS && CONFIG_SYSTEM_NXINIT)
and CMake (nuttx_add_romfs()) builds, matching qemu-armv7a/qemu-armv8a.
rc.sysinit and rcS are left in place: on rv-virt both are empty
license-only shells still referenced unconditionally by boards/Board.mk
for the kernel-build and pnsh/pnsh64 configs.
CONFIG_FS_BINFS=y is added with a binfs mount at CONFIG_PATH_INITIAL
(pre-existing "/system/bin") in
qemu_rv_boardinit.c:board_late_initialize() (gated on CONFIG_FS_BINFS,
so the block and the CONFIG_PATH_INITIAL reference compile out when
binfs is not selected).
Rationale: nxinit resolves the "sh" service via posix_spawnp() ->
exec_spawn() -> load_module(); with CONFIG_LIBC_ENVPATH that walks $PATH
via envpath_next() and stat()s each "$dir/sh" candidate, so it never
reaches the builtin binfmt loader unless a real directory entry exists.
CONFIG_PATH_INITIAL is left at its pre-existing "/system/bin"; mounting
binfs there (rather than repointing PATH) makes "sh" resolvable while
keeping the defconfig delta minimal. This never surfaced under nsh_main,
which runs nsh_consolemain() inline without spawning by relative path.
Equivalent to the binfs mount already present in boards/sim's
sim_bringup.c (which mounts at /bin, its own PATH_INITIAL).
smp and smp64 additionally re-enable binfmt: their CONFIG_DEFAULT_SMALL=y
default pulls in CONFIG_BINFMT_DISABLE=y, which blocks
CONFIG_LIBC_EXECFUNCS (thus CONFIG_SYSTEM_NXINIT) and would otherwise
fail to link with "undefined reference to init_main". Same fix
boards/sim used for its affected configs.
citest/citest64 also carry their pre-existing explicit
CONFIG_INIT_STACKSIZE value (3072/4096) over to
CONFIG_SYSTEM_NSH_STACKSIZE: under nxinit "sh" is a separate spawned
child sized by SYSTEM_NSH_STACKSIZE, which otherwise dropped to the
2048 default and overflowed (citest64 crashed running `ps`). Every
other switched config that had an INIT_STACKSIZE override already had a
matching SYSTEM_NSH_STACKSIZE one.
All 23 switched configs were booted (not just compiled) and show
init_main as the parent with sh as its Running child in `ps` (see the
PR description for logs).
Assisted-by: opencode-agent/claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
The mcuboot-loader image overflows its flash region once the FAT deferred-delete change is applied. Long filename support is not needed by the bootloader, which boots from flash areas and never opens FAT files by long name, so disable CONFIG_FAT_LFN to reclaim the space while keeping short filename support intact.
Signed-off-by: Arnav Sharma <2006arnavsharma@gmail.com>
This restores the entrypoint switch from commit
7cc6707a76 ("boards/esp32s3-xiao: switch
defconfigs to nxinit entrypoint"), reverted in 76b90e02cbe4967193
b620abcb1efb9f6b3f8f5b after a real-hardware regression report on
Seeed XIAO ESP32-S3 (board hangs, no USB console), and fixes the
actual root cause this time instead of just reverting it.
Root cause: the shared boards/xtensa/esp32s3 init.rc starts the
interactive console as a plain "sh", which, unlike nsh_main's
nsh_consolemain(), never registers/connects the CDC-ACM gadget this
board uses as its console (CONFIG_CDCACM_CONSOLE=y, no
CONFIG_DEV_CONSOLE). Restoring the previous commit's entrypoint switch
on its own is therefore not sufficient - it would just reintroduce the
same regression, so that commit is folded into this one rather than
kept as a separate, individually broken step.
Fix, using the "console" service option added to nxinit by a companion
apps change:
- init.rc: bring up the console gadget once, unconditionally, before
any service starts, via "exec -- sercon" (apps/system/cdcacm already
implements exactly this and depends on neither nxinit nor nsh); flag
the "console" service with the new "console" option so its stdio is
connected to the (now registered) gadget device.
- esp32s3-xiao's usbnsh/combo defconfigs: add CONFIG_SYSTEM_CDCACM=y so
sercon is actually built in. Verified with "make savedefconfig"
against both defconfigs (byte-identical, no manual edits beyond the
generated diff).
Verified end to end on real Seeed XIAO ESP32-S3 Sense hardware
(usbnsh): after this change the board enumerates its NuttX CDC-ACM
gadget on a normal reset and boots to an interactive nsh session
spawned by nxinit ("ps" shows init_main as PID 2, parent of "sh").
Assisted-by: Kiro:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Nothing copies .data on a RAM/remoteproc image (CONFIG_BOOT_RUNFROMISRAM=y),
so an LMA distinct from the VMA loads initialised data where the code never
reads it. _sidata was taken before .init_section, putting the load address
sizeof(.init_section) below the run address.
That section is empty in the in-tree configurations, so the fault is latent
today and this change is a no-op for them; it appears as soon as anything lands
in .init_array.
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
The in-tree esp32s3-xiao board bringup never wires up Wi-Fi at all --
unlike esp32s3-devkit/esp32s3-eye, it has no
`#ifdef CONFIG_ESPRESSIF_WIFI` include of esp32s3_board_wlan.h and no
call to board_wlan_init(). Add both, mirroring those boards' pattern
and placement exactly.
On its own this is not enough for a board that also uses CONFIG_PM:
Wi-Fi's PHY/RF calibration inside board_wlan_init() cannot tolerate
the clock gating of PM_STANDBY (light sleep). If the idle task enters
light sleep while phy_init's calibration is still running -- which the
greedy governor is free to do the moment the CPU goes idle during
driver init -- the calibration hangs forever waiting on a clock that
just stopped. Confirmed on real XIAO ESP32-S3 hardware: with
CONFIG_PM + CONFIG_ESPRESSIF_WIFI both enabled and no guard, boot got
stuck 100% of the time right after the "net80211 rom version" line,
before phy_init ever printed, and never reached NSH -- reproducible
across repeated flashes, 50s+ waits, not even responding to a UART
wakeup keypress (a genuine hang, not quiet sleep).
Fixed by holding a stronger PM lock than PM_STANDBY for the duration
of board_wlan_init(): pm_stay(PM_IDLE_DOMAIN, PM_IDLE) blocks
PM_STANDBY/PM_SLEEP while still allowing normal CPU idle, and
pm_relax() releases it immediately after, restoring whatever floor the
board's own PM policy holds otherwise. Confirmed fixed on the same
hardware: boots clean to NSH with Wi-Fi + PM enabled together, `ps`
shows the wifi/netdev-wlan0 kernel threads running, and `wapi scan`/
`ifup wlan0` work normally.
esp32c3-devkit and esp32c6-devkit also combine CONFIG_PM with Wi-Fi,
but don't need this guard today: both call board_wlan_init() well
before esp_pmconfigure() (which is what actually arms the PM governor)
runs near the end of bringup, so PM isn't active yet during their
Wi-Fi init. This board's PM handling begins earlier in bringup, so the
two can race here.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Assisted-by: Claude:claude-sonnet-5
gotindex named the .got section header, and every user then reached through
shdr[] for what it actually wanted. Only one of the five wanted the index.
gotbase and gotsize say it directly. gotsize is the extent of .got and is
also what says the object has one, and gotbase is where the GOT ended up:
the placed address of .got for an ordinary object, or DT_PLTGOT for an FDPIC
one, which libelf_bind() already reads. Both are set in libelf_loadfile(),
after the sections are placed, so gotbase is the address the object will be
read at rather than the one it was linked for.
The GOT walk in libelf_loadfile() now runs only when there is a base, which
also keeps it off an FDPIC object. An FDPIC object's sections are never
placed, so .got carried a link time sh_addr there, and the walk read and
wrote through it. Its GOT is relocated through its own relocations.
The check that gates libelf_xipacquire() runs before the load, when neither
field is set, so it looks the section up by name. It hands the index it
found to libelf_loadfile(), which is the only reason that function takes
one: the object is searched once, not twice.
One behaviour changes: a .got that exists but is empty now reads as no GOT.
There is nothing for any of the five users to do with an empty one.
Built for pimoroni-pico-2-plus with CONFIG_PIC, CONFIG_ELF and
CONFIG_LIBC_ELF, and for mps3-an547:bl, which is the board that read the
index. Run on QEMU with mps3-an547:picostest, which loads PIC ELF modules
from a romfs: hello prints, and ostest reaches the timed mutex test, the
same as before the change.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Add a CDC/ACM (console) + USB fastboot (ADB "fastboot" personality)
composite device to the shared rp2040_composite.c board glue, and a
new "fastboot_usb" defconfig for waveshare-rp2040-zero and
waveshare-rp2040-lcd-1.28.
- boards/arm/rp2040/common/src/rp2040_composite.c: add a third
composite slot for CONFIG_USBADB (covers both plain ADB and, with
CONFIG_USBFASTBOOT, the "fastboot" personality of the same driver)
alongside the existing MSC/CDC-ACM slots. While adding this,
fixed a latent bug: the CDC/ACM block never advanced ifnobase/
strbase after filling in its own slot, because CDC/ACM used to
always be the *last* device in the composite (nothing downstream
ever needed the incremented values). Now that a device can follow
CDC/ACM, the missing increment caused the fastboot interface to be
assigned the same USB interface number as CDC/ACM's control
interface (both 0), which the Linux kernel rejects with "Duplicate
descriptor for config 1 interface 0 altsetting 0, skipping" and
drops the fastboot interface entirely (confirmed via lsusb -v and
disassembly of the generated board_composite_connect() code).
- boards/arm/rp2040/waveshare-rp2040-zero/configs/fastboot_usb and
boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/fastboot_usb:
new defconfig booting directly into fastbootd
(CONFIG_INIT_ENTRYPOINT="fastbootd_main", no nsh) which brings up
the CDC/ACM + fastboot composite via
CONFIG_SYSTEM_FASTBOOTD_USB_BOARDCTL as soon as fastbootd starts,
so the CDC/ACM sub-interface still provides a console for boot/
fastbootd log visibility without requiring a wired UART, while the
fastboot vendor interface is what `fastboot devices`/`getvar` talk
to.
Assisted-by: OpenCode:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Drives the speed of the four application cores. The rate is set to any
of the operating points the vendor validates, all of which share a core
voltage, so this touches no regulator.
The cores run from the PLL being reprogrammed, so they park on a slower
clock first, through a selector the vendor names as glitch free. While
parked the PLL is stopped, given new dividers, restarted and watched
until it locks; if it never locks the cores stay parked, since returning
them to an unlocked PLL does not fail safely.
Above a gigahertz the bus ratio must be two to one before the cores
return: the bus fabric does not reach beyond about eight hundred
megahertz. That is the one step in the sequence software cannot recover
from, so the mux is moved before the ratio.
The rate is measured rather than derived. The cores are counted against
the crystal derived time counter and the result reported beside what the
clock tree computes, because the manual and the vendor's code number the
CPU PLL's outputs differently. The core selector's parent is
cpupll_fout1, and the three CPU PLL outputs are marked
CLK_GET_RATE_NOCACHE since this driver reprograms that PLL at run time.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Add reset_usb_boot ROM function typedef and wire it into
board_reset() so that 'nsh> reboot bootloader'
(BOARDIOC_SOFTRESETCAUSE_ENTER_BOOTLOADER) on RP2040 boards enters
BOOTSEL USB mass-storage mode directly, matching the behavior
already available on rp23xx boards. All other status values keep
the existing up_systemreset() behavior.
This affects all boards under boards/arm/rp2040/common (pico,
pico-w, feather-rp2040, xiao-rp2040, w5500-evb-pico, etc.) since
the change is in the shared board_reset() implementation.
Assisted-by: GitHubCopilot:claude-4.6-opus
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
The console divisor was computed from 198144000, a figure with no source
in the manual, the vendor tree or Linux, all of which give the low speed
peripheral clock as 200 MHz. The clock tree now reports lsp_uart0_pclk
at 200 MHz, and section 12.4.3.2 makes that clock the UART's baud
reference.
Also enable the fractional divisor. These are DesignWare UARTs with DLF
implemented, four bits wide at offset 0xc0, which is where
UART_DLF_OFFSET lands once scaled by this board's register increment.
Section 12.4.3.2 works the same example at the same 200 MHz.
At 115200 the error goes from 1.41% to 0.006%. The old figure with the
old divisor was tolerable; the margin only gets worse at higher rates.
DEBUG_CLK and DEBUG_CLK_ERROR are enabled so a clock that fails to
register is reported.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The architecture registers the clock tree before the board runs, and every
driver the board brings up afterwards depends on it. Report what
registered, so a tree that came up short is visible without a debug build.
eic7700x_clk_count() supplies the numbers; /proc/clk has the tree itself.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
A C++ module with a static object does not link. GCC registers each such
object's destructor with __cxa_atexit(dtor, obj, &__dso_handle), and
__dso_handle comes from crtbegin, which a module does not link:
hello++3.cxx:119: undefined reference to `__dso_handle'
It is reachable today with CONFIG_PIC, where a module is linked as an
executable and the symbol has to resolve. Without it the link is
relocatable, the symbol stays undefined and nothing complains until
something makes it resolve.
-fno-use-cxa-atexit registers the destructors with atexit() instead, which
puts them in .fini_array. That is also where libelf_uninit() looks for them
when the module is unloaded, so the flag that makes the link work is also
the flag that makes the destructors run.
The option goes wherever CXXELFFLAGS is defined, which is the architecture
Toolchain.defs and the boards that reassign it. The toolchains that are not
GCC or Clang are left alone: ceva, tricore, z16 and the z80 family.
The CMake build sets it once, next to where the architecture elf.cmake is
included. A generator expression keeps it off the C compiles, because the
option is valid for C++ alone and GCC warns about it otherwise, and the
compiler id gates it so that a toolchain which is neither GCC nor Clang does
not see it. It cannot go in the toolchain file itself: CMake reads that file
again inside try_compile, in a project that has not included the NuttX
extensions, so the call is an unknown command there.
Reproduced with apps/examples/elf on mps3-an547:picostest with CONFIG_PIC
enabled: hello++3 fails to link before and links after.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
nuttx-apps PR #3763 adds "default 4096 if LIBC_PRINT_EXTENSION" to
CONFIG_UORB_STACKSIZE. Both lckfb-szpi-esp32s3/qmi8658 and
esp32s3-ws-lcd128/imu-qmi8658 already set CONFIG_UORB_STACKSIZE=4096
explicitly, which now matches the new default and makes the line
redundant, so savedefconfig drops it -- causing the CI defconfig-sync
check (testbuild.sh -R) to flag these files as stale and fail the
xtensa-03 job.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Assisted-by: Claude:claude-sonnet-5
The bootloader image has no linked HPWORK or LPWORK consumers, but
enabling both queues pulls unused scheduler code into its constrained
OCRAM region.
Disable the predefined work queues and let deferred memory reclamation
fall back to the idle thread.
Assisted-by: Codex:GPT-5
Signed-off-by: DuoYuWang <thirteenking.wang@gmail.com>
This commit add support to GD32VW553-HMQ board based on GigaDevice
GD32VM553K_START as base.
No AI used for this board, the but GD32VM553K_START was developed
by Jorge Guzman with help from Claude Code.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
This reverts commit 7cc6707a76.
Felipe Moura de Oliveira reported on the dev mailing list that this
commit hangs boot on real Seeed XIAO ESP32-S3 Sense hardware (chip
rev v0.2): both defconfigs (combo, usbnsh) never reach nx_start after
a normal reset (no console output, no USB enumeration; only ROM
download mode via the BOOT strap pin responds). JTAG (OpenOCD + GDB)
shows the core statically stuck inside the chip boot ROM address
range (0x40034000-0x40048000), with nx_start never reached at its
own address (0x42011068) in that build. Reverting only this commits
defconfig changes on top of current master fixes the boot.
Local static analysis (before/after build product comparison via
esptool image_info and readelf -S) ruled out image size/segment
count as the cause: both binaries have 3 segments, identical IRAM
segment address/size byte-for-byte, and the flash-mapped code/data
growth from this change is ~14.7KB total against an 8MB flash
budget. No hardware matching the reported board was available
locally to reproduce or bisect further; reverting to unblock master
per the reporters request while root cause is investigated with
real hardware access.
Reference: https://www.mail-archive.com/dev@nuttx.apache.org/msg15063.html
Assisted-by: Kiro:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Switch every qemu-armv7a defconfig whose init entry point was nsh_main
(6 configs: full, gdbstub, nsh, rpproxy, rpserver, smp) to nxinit
(init_main). nsh now runs as a "console sh" service started by init.rc
instead of being the top-level init task.
Each switched defconfig only gains the nxinit-essential keys (minimal
delta):
- CONFIG_INIT_ENTRYPOINT="init_main"
- CONFIG_SYSTEM_NXINIT=y plus its Kconfig deps not already set:
CONFIG_EXPERIMENTAL, CONFIG_LIBC_EXECFUNCS, CONFIG_SCHED_CHILD_STATUS
(depends on CONFIG_SCHED_HAVE_PARENT)
- CONFIG_ETC_ROMFS=y / CONFIG_FS_ROMFS=y to ship init.rc via ROMFS
No stack-size overrides: INIT_STACKSIZE/SYSTEM_NSH_STACKSIZE keep their
Kconfig defaults.
Add boards/arm/qemu/qemu-armv7a/src/etc/init.d/init.rc, shipped via ROMFS
in the Make build (RCSRCS) and CMake (nuttx_add_romfs()), gated on
CONFIG_ETC_ROMFS && CONFIG_SYSTEM_NXINIT.
Testing: qemu-armv7a:nsh (and smp with -smp 4) boot into nxinit with nsh
spawned as its service (init task = init_main, sh = its child), confirmed
via qemu-system-arm in an earlier run of this series. Note: current
apache/master fails to build qemu-armv7a locally this round (missing
arm_timer.h) independent of this change.
Assisted-by: opencode-agent/claude-opus-4-8
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Switch every qemu-armv8a defconfig whose init entry point was nsh_main
(20 configs) to nxinit (init_main). nsh now runs as a "console sh"
service started by init.rc instead of being the top-level init task.
Each switched defconfig only gains the nxinit-essential keys (minimal
delta):
- CONFIG_INIT_ENTRYPOINT="init_main"
- CONFIG_SYSTEM_NXINIT=y plus its Kconfig deps not already set:
CONFIG_EXPERIMENTAL, CONFIG_LIBC_EXECFUNCS, CONFIG_SCHED_CHILD_STATUS
(depends on CONFIG_SCHED_HAVE_PARENT)
- CONFIG_ETC_ROMFS=y / CONFIG_FS_ROMFS=y to ship init.rc via ROMFS
No stack-size overrides: INIT_STACKSIZE/SYSTEM_NSH_STACKSIZE keep their
Kconfig defaults (DEFAULT_TASK_STACKSIZE, already 8192 on this board).
Add boards/arm64/qemu/qemu-armv8a/src/etc/init.d/init.rc, shipped via
ROMFS in the Make build (RCSRCS) and CMake (nuttx_add_romfs()), gated on
CONFIG_ETC_ROMFS && CONFIG_SYSTEM_NXINIT. Omitting this ROMFS plumbing
causes a link-time "undefined reference to romfs_img".
Testing: qemu-armv8a:nsh (and nsh_smp with -smp 4) boot into nxinit with
nsh spawned as its service (init task = init_main, sh = its child),
confirmed via qemu-system-aarch64 in an earlier run of this series. The
removed explicit 8192 stack sizes equal this board's DEFAULT_TASK_STACKSIZE,
so runtime behavior is unchanged. Note: current apache/master fails to
build locally this round (empty -Wstack-usage=, missing libfdt.h)
independent of this change.
Assisted-by: opencode-agent/claude-opus-4-8
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Switch every sim/sim/sim defconfig whose init entry point was nsh_main
(81 configs) to nxinit (init_main). nsh now runs as a "console sh"
service started by init.rc instead of being the top-level init task.
Each switched defconfig only gains the nxinit-essential keys (minimal
delta, regenerated so no unrelated options leak in):
- CONFIG_INIT_ENTRYPOINT="init_main"
- CONFIG_SYSTEM_NXINIT=y plus its Kconfig deps that were not already set:
CONFIG_EXPERIMENTAL, CONFIG_LIBC_EXECFUNCS, CONFIG_SCHED_CHILD_STATUS
(which depends on CONFIG_SCHED_HAVE_PARENT)
- CONFIG_ETC_ROMFS=y / CONFIG_FS_ROMFS=y to ship init.rc via ROMFS
No stack-size overrides are added: INIT_STACKSIZE and SYSTEM_NSH_STACKSIZE
keep their Kconfig defaults (DEFAULT_TASK_STACKSIZE).
Five configs (dynconns, module, module32, sotest, sotest32) had
CONFIG_BINFMT_DISABLE=y, which blocks CONFIG_LIBC_EXECFUNCS and thus
CONFIG_SYSTEM_NXINIT. Since nxinit spawns services via exec(), binfmt is
re-enabled in those five. They also enable CONFIG_LIBC_ENVPATH but did
not ship a /bin, so nxinit's posix_spawnp("sh") resolved via PATH and
failed with ENOENT ("Error Starting service 'console': 2"). Add
CONFIG_FS_BINFS=y and CONFIG_PATH_INITIAL="/bin" to those five so the
builtin apps are visible under /bin and the console service starts,
matching the working sim:nsh config.
citest additionally needed CONFIG_ETC_ROMFSDEVNO=1 (matching the 53
other sim configs that already set it to avoid the same collision):
sim_registerblockdevice() (arch/sim/src/sim/sim_blockdevice.c, called
from up_initialize() before any application task starts) unconditionally
registers a FAT ramdisk at /dev/ram0 whenever CONFIG_FS_FAT is set, and
citest is one of the few switched configs with CONFIG_FS_FAT=y that had
never overridden CONFIG_ETC_ROMFSDEVNO away from its Kconfig default of
0. With nxinit, romdisk_register() for /etc's ROMFS at that same minor
number then fails with -EEXIST and nxinit aborts with "Error Opening
/etc/init.d/init.rc" since it treats a missing init.rc as fatal;
nsh_main() silently tolerated the identical failure before this switch
(logs "init: open failed: 2" and continues to the nsh prompt), so the
/etc mount had actually never worked for citest even pre-nxinit.
Add boards/sim/sim/sim/src/etc/init.d/init.rc (registers a "console sh"
service guarded by CONFIG_SYSTEM_NSH; "on init" starts it), shipped via
ROMFS in the Make build (RCSRCS) and CMake (nuttx_add_romfs()), both gated
on CONFIG_ETC_ROMFS && CONFIG_SYSTEM_NXINIT so non-nxinit configs are
unaffected.
Switching to nxinit means nsh_main()/nsh_initialize() (which used to run
/etc/init.d/rc.sysinit and rcS to mount /tmp and /data) no longer runs on
the 46 sim configs that already had CONFIG_ETC_ROMFS=y on master, so
those mounts would otherwise be lost. /bin (binfs) and /proc (procfs) are
unaffected: sim_bringup() (called from board_late_initialize(), before
any entrypoint task starts, independent of nsh_main/init_main) already
mounts them unconditionally on master, and this PR does not touch that
file. init.rc's "on init" action reproduces the rest of rc.sysinit's
mounts (tmpfs, or the FAT-backed /tmp ramdisk via mkrd + mkfatfs + mount
for boards without CONFIG_FS_TMPFS) plus the hostfs /data mount that
used to live in rcS, inlining them directly instead of spawning the
standalone rcsysinit/rcS scripts through a "service ... oneshot"
indirection. nxinit has no builtin mount/mkrd/mkfatfs yet, so each of
these commands still resolves through its posix_spawnp() sh fallback;
that limitation is unchanged by this PR and is left for a follow-up
(either a native mount() call in sim_bringup() for the fixed-path
mounts, or a builtin in nxinit). The 6 configs that also enable
CONFIG_FS_FAT get an explicit CONFIG_ETC_FATDEVNO=2 so this ramdisk does
not collide with /etc's romdisk.
Now that every sim nsh_main + CONFIG_ETC_ROMFS config has switched to
nxinit, boards/sim/sim/sim/src/etc/init.d/rcS and rc.sysinit are dead
code: no remaining sim config calls nsh_initialize() (the only caller of
those scripts), so remove both files outright and drop them from
boards/sim/sim/sim/src/CMakeLists.txt and Makefile's ROMFS RCSRCS list
(init.rc is shipped instead, as above, only when CONFIG_SYSTEM_NXINIT=y).
The remaining ROMFS-enabled sim configs whose entrypoint isn't nsh_main
(nxlines/nxwm/toybox) never executed rcS/rc.sysinit either (their
entrypoint never calls nsh_initialize()), so they lose nothing but a few
unused bytes from their ROMFS image; sim:nxlines was rebuilt to confirm
it still links and boots with an empty etc/init.d/.
init.rc also uses <nuttx/macro.h>'s CONCATENATE() instead of a local
CONCAT_()/CONCAT() pair, matching existing NuttX convention instead of
duplicating a macro the tree already provides.
sim:windows and sim:windows64 are excluded and stay on nsh_main: they
build under MSVC in CI, and CONFIG_SYSTEM_NXINIT pulls in
apps/system/nxinit/action.c, which fails to compile under MSVC because
list_peek_head_type() (include/nuttx/list.h) uses a GCC
statement-expression the MSVC C compiler does not support; separately,
CONFIG_ETC_ROMFS routes them through nuttx_add_romfs()'s POSIX-shell
genromfs/xxd/sed custom build step, which cmd.exe cannot parse either.
Both are pre-existing MSVC gaps in nxinit/the ROMFS CMake helper, not
something this defconfig-only PR should fix, so these two configs are
left on nsh_main.
Testing (sim, host gcc): sim:nsh boots into nxinit with nsh spawned as
its service (init task = init_main, sh = its child), and now shows the
same five mount points as master (/bin /data /etc /proc /tmp), matching
the pre-switch nsh_main baseline; /data round-trips a write to the host
filesystem. The five binfmt configs reach an interactive nsh prompt
(help/uname work) instead of failing to start the console; e.g.
sim:module:
BEFORE fix: Error Starting service 'console': 2
AFTER fix: nsh> help / nsh> uname -a (console up)
init.rc's inlined FAT/tmpfs mount was verified by preprocessing it with
cpp under both CONFIG_FS_FAT and CONFIG_FS_TMPFS: the expansion matches
rc.sysinit's mount sequence (CONCATENATE() resolves to /dev/ram2, etc.).
sim:citest specifically verified with gdb: before the ETC_ROMFSDEVNO fix,
register_blockdriver("/dev/ram0") is called twice (once by
sim_registerblockdevice() from up_initialize(), once by nx_romfsetc());
the second call returns -EEXIST and nxinit aborts. After setting
CONFIG_ETC_ROMFSDEVNO=1, sim:citest boots cleanly into nxinit (ps shows
init_main waiting on its child sh, matching sim:nsh), and the compiled
ROMFS image contains only init.rc. sim:nxlines, a non-nxinit
CONFIG_ETC_ROMFS config, was rebuilt to confirm it still links and boots
with the now-empty etc/init.d/ (rcS/rc.sysinit removed).
Assisted-by: opencode-agent/claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba timer driver
(arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0
(TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC
masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two
32-bit basic LTIM timers at 0x40819200 / 0x40819400, 32.768 kHz,
APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h
/ sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build
hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in
by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up
registration and a timer defconfig. The shared driver is unchanged.
TIM0 is left untouched because the boot ROM claims it as the always-on
system timer; reprogramming it would break every SDK delay.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba timer driver
(arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0
(TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC
masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two
32-bit basic LTIM timers at 0x40808200 / 0x40808400, 32.768 kHz,
APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h
/ sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build
hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in
by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up
registration and a timer defconfig. The shared driver is unchanged.
TIM0 is left untouched because the boot ROM claims it as the always-on
system timer; reprogramming it would break every SDK delay.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a parameterised NuttX timer lower-half for the Realtek Ameba
general-purpose timers, sitting on the SDK fwlib RTIM register layer and
registered at /dev/timerN. The shared driver
(arch/arm/src/common/ameba/ameba_timer.c) reads a per-chip instance
table (ameba_timer_chip.h) for each timer's base, input clock, RCC gate
masks and IRQ; the period is programmed directly in microseconds and
converted to the 32-bit auto-reload with one clkfreq formula.
On the pke8721daf two of the 32.768 kHz "basic" (LTIM) timers are
exposed: /dev/timer0 is TIM1 and /dev/timer1 is TIM2. TIM0 is left
untouched because the boot ROM claims it as the always-on system timer
(SYSTIMER); reprogramming it would break every SDK delay. The RTIM
time-base entry points resolve to ROM, while the interrupt-clear and
period-change helpers come from the fwlib RAM source ameba_tim.c (shared
with the PWM driver).
Verified on hardware with examples/timer against both devices: the
update interrupt fires at the requested 1 s interval (measured with the
independent ROM SYSTIMER = 32768 ticks = 1.000 s).
Also whitelist the vendor RTIM_ symbol prefix in tools/nxstyle.c,
alongside the existing RCC_/SYSTIMER_ Ameba SDK entries.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
NETDEV_CAN_BITRATE_IOCTL, NETDEV_CAN_FILTER_IOCTL and
NETDEV_CAN_STATE_IOCTL guarded identical option blocks, and every
SIOCxCANxxx case in netdev_ifr_ioctl() forwarded a member of the same
ifr_ifru union to d_ioctl(). One option and one case block now cover
all of the CAN commands; drivers and defconfigs are updated to the
new name.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
mtd_partition(mtd, firstblock, nblocks) takes the partition offset and
size in units of the underlying device "blocks" (geo.blocksize), not
erase blocks. Several board drivers accumulated partoffset and computed
the partition size in erase-block units and passed them straight to
mtd_partition(), so on devices where blocksize != erasesize (W25/SST25:
256B vs 4KB, SAMD5E5 progmem: 512B vs 8KB) every partition came out
erasesize/blocksize (16x) too small and misaligned.
Convert partoffset and partszbytes to geo.blocksize units at the
mtd_partition() call site while keeping the erase-block accumulation.
Affected boards:
- stm32f103-minimum (W25)
- at32f437-mini (W25)
- stm32f429i-disco (SST25F064, enabled in the extflash defconfig)
- metro-m4 (SAMD5E5 progmem)
Also fix pre-existing nxstyle violations in the touched files so the
change passes checkpatch (see CONTRIBUTING.md).
Assisted-by: DeepSeek Harness:deepseek-v4-flash
Signed-off-by: rongbaichuan <rongbaichuan1027@163.com>
The Tab5 ships in two hardware variants and the board supported only
one of them. The earlier units carry an ILI9881C panel and a GT911
touch controller, the later ones a ST7121/ST7123 panel and a ST7123
touch controller, and the two always come as a pair. On an earlier
unit the panel stays lit but black, and the touch bring-up fails with
"failed to register ST7123: -5".
Add the ILI9881C initialization table, taken from the Espressif BSP,
along with the display timings it needs, which differ from the ST7123
ones in the DPI clock (60 MHz instead of 70 MHz) and in every porch.
The panel identification lives on command page 1 and is read and
logged during bring-up, so the boot log says which panel answered.
Add the GT911 to the touch controller choice. These units have a
pull-up to 3V3 on the touch interrupt line that keeps the controller
from scanning, so the line is driven low instead of being used as an
interrupt, and contacts are picked up when the device is read. The
controller identification is logged the same way.
Split esp32p4_touch.c into one file per controller, which is how the
panels are already handled, and document both variants together with
the I2C scan that tells which one is fitted. The defaults are
unchanged, so an existing configuration still selects the ST7121
panel and the ST7123 touch controller.
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
The XIAO ESP32-S3 Sense's onboard microSD slot (Seeed XIAOML Kit) is
wired to SPI2 through the GPIO matrix: SCK=GPIO7, MOSI=GPIO9,
MISO=GPIO8 (confirmed against espressif/arduino-esp32's
XIAO_ESP32S3/pins_arduino.h) and CS=GPIO21 (confirmed against this
project's own working xiaoml_bench_logger.ino, which tries CS
candidates {21, 3} in that order -- GPIO3 is a documented fallback,
not the real pin; a Seeed wiki page that names GPIO3 as CS turned out
to be wrong and was the initial, unsuccessful attempt here).
Wires up board_sdmmc_spi_initialize() (common esp32s3 board code,
CONFIG_MMCSD_SPI) into this board's bringup, and adds the
esp32s3_spi2_status() callback (SPI_STATUS_PRESENT for SPIDEV_MMCSD(0))
that esp32s3-devkit and other in-tree boards already provide -- the
esp32s3-xiao board had no SPI board file at all before this.
Validated on the bench: CMD0/CMD41/CMD58 handshake succeeds, SD ver2
card identified (SanDisk 32GB, 62333952 sectors), mounts as vfat,
survives umount+remount with a written file intact.
Needed board defconfig additions (not included in this NuttX-tree
commit; see the 61680_FW project repo for the board config that turns
this on):
CONFIG_ESP32S3_SPI2=y
CONFIG_ESP32S3_SPI2_CSPIN=21
CONFIG_ESP32S3_SPI2_CLKPIN=7
CONFIG_ESP32S3_SPI2_MOSIPIN=9
CONFIG_ESP32S3_SPI2_MISOPIN=8
CONFIG_MMCSD=y
CONFIG_NSH_MMCSDSPIPORTNO=2
CONFIG_FS_FAT=y
CONFIG_FAT_LFN=y
CONFIG_FAT_LCNAMES=y
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: Felipe Moura <mouraf@fiteclabs.org.br>
board_buttons() loops over the four buttons but read the GPIO of
g_buttons[BUTTON_BTN1] on every iteration, so all four bits of the
returned set reflected the state of button 1 alone.
Matches the equivalent loop in nrf52840-dk's nrf52_buttons.c.
Signed-off-by: AlmAck <gluca86@gmail.com>
Adopt the zbus message bus on the linum-stm32h753bi (first adopter
board):
- scripts/flash.ld: include the iterable sections common fragments
(2 lines: common-rom.ld inside .text, common-ram.ld inside .data).
- configs/zbus/defconfig: board configuration enabling zbus with all
observer types, the zbus example and its cmocka test suite
(./tools/configure.sh linum-stm32h753bi:zbus).
- Board documentation: describe the new configuration.
Validated on hardware: the 16-test cmocka suite passes twice in the
same boot and the zbus example produces the expected output.
Assisted-by: Claude Code
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
No driver exists for this exact chip. lsm6dsl.c is the closest
register-compatible match but is the deprecated legacy char-device
style; lsm6dso32_uorb.c is the closest uORB-style match but is for a
different chip variant. The new driver borrows lsm6dso32_uorb.c's
structure (dual sensor_lowerhalf_s, raw I2C_TRANSFER helpers) and
lsm6dsl.h's register map -- fixing a bug in the header it was ported
from along the way: LSM6DSL_FIFO_CTRL2_SHIFT is defined as 255 instead
of 0.
Delivery mode is chosen the same way mpu6050 does: kthread polling by
default, or interrupt-driven if the board supplies attach(). Unlike
the earlier lsm6dso32-style design this went through first -- one INT
pin and one activate()/interrupt path per sub-sensor -- the shipped
version uses a single shared INT pin for both, mirroring mpu6050's own
one-handler-one-worker design (#19601) instead. The two-independent-
paths version worked for accel alone but was intermittently broken for
gyro: activate() sometimes never actually turned CTRL2_G on even
though the interrupt-enable bit was written correctly, and other times
the whole console hung -- a real race, never conclusively root-caused
on a serial console with no JTAG available. The LSM6DS3TR-C supports
OR'ing both DRDY_XL and DRDY_G onto one pin via independent enable
bits in that pin's INTn_CTRL register, so there was no need for two
paths in the first place: one ISR times the burst, one HPWORK worker
reads OUT_TEMP_L..OUTZ_H_A (14 contiguous bytes covering temp, gyro
and accel in one I2C transaction) and pushes whichever topic(s) are
currently subscribed. activate() now just flips each sub-sensor's own
bit in the shared register instead of running its own attach.
On the XIAO ESP32-S3 with Seeed's IMU Breakout Board, INT1/INT2 route
to GPIO3/GPIO4 (confirmed from the breakout board's schematic, not
guessed). Only INT1/GPIO3 is wired up, since one pin is now enough;
GPIO4/INT2 is documented as available but unused.
Also: CTRL1_XL's FS_XL bits were never actually written to match the
driver's own software default (4g) -- registration set the in-memory
value but the chip stayed at its 2g reset default until a caller
issued an explicit SNIOC_SETFULLSCALE. register() now writes it.
Validated on the bench, both modes, reproduced across multiple fresh
reboots: WHO_AM_I reads 0x6a, sensor_accel0/sensor_gyro0 stream
continuously. Interrupt mode delivers ~300 samples of each per 6s
window with shared timestamps down to the microsecond between the two
topics per event, confirming both come from the same burst read.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
This commit introduces EDID reading and parsing to the JZ4780 display
driver, replacing hardcoded resolution limits with dynamic mode selection
based on the connected display's capabilities.
Specific changes include:
- Implemented I2C DDC master communication for the HDMI controller to
read EDID blocks from monitors.
- Added dynamic mode selection to calculate bandwidth and pick the best
supported resolution, prioritizing the EDID preferred mode.
- Dynamically allocated framebuffer bounds (g_planeinfo and g_videoinfo)
based on parsed EDID dimensions.
- Configured GPIO pin multiplexing for HDMI power, DDC, and control pins
(POWER_EN, CEC, SCL, SDA) to enable display power and communication
on the CI20 board.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x4080AD80,
CPU0_NS_WDG IRQ 69, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x40801D80,
KM4TZ_NS_WDG IRQ 52, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Also corrects the RTL8720F row in the rtl8721dx chip-header reference
table (the non-secure system WDG IRQ is KM4TZ_NS_WDG = 52).
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a NuttX watchdog lower-half for the Ameba KM4 non-secure system
watchdog (WDG2), registered as /dev/watchdog0. The fwlib WDG API is
ROM-resident, so no board.mk change is needed.
The hardware cannot be stopped once enabled, so stop() is emulated via
the early interrupt (EI) auto-refreshing the counter, and capture()
delivers a pre-timeout callback through the same EI. The EI has a
three-part timing contract, all handled here: it must be armed with
EIMOD=ENABLE at WDG_Init, its EIE gate only takes effect after
WDG_Enable, and -- because the EI is level-based -- a pure capture path
must mask EIE after the one-shot callback to avoid re-entrant storming
while the reset is pending. The EI flag is cleared twice per the slow
WDG clock.
Per-chip base address and IRQ live in ameba_wdg_chip.h so the shared
driver needs no change to port to another Ameba IC.
Verified on pke8721daf: timeout reset (BOOT REASON WDG2), stop()
suppressing the reset, and capture() firing ~EICNT ms before the reset.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
The esp32s3-devkit:usbmsc config uses CONFIG_ESPRESSIF_SIMPLE_BOOT, so
the image is packaged with "esptool elf2image --ram-only-header". With
esptool v5.2.0, that path asserts that each flash segment satisfies
(f.tell() + 8 + BOOTLOADER_FLASH_OFFSET) % IROM_ALIGN
== segment.addr % IROM_ALIGN
When .flash.text lands right on a 64 KB (IROM_ALIGN) boundary the
assertion cannot be satisfied and elf2image fails with AssertionError,
even though NuttX itself links cleanly.
usbmsc is a plain C test and does not need the C++ runtime. Disabling
CONFIG_HAVE_CXX / CONFIG_HAVE_CXXINITIALIZE moves .flash.text off the
IROM_ALIGN boundary so the SIMPLE_BOOT image can be generated, without
changing the boot mode or the test's intent.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
Adds GPIO defconfig on M5Stack Tab5. The example has one GPIO output
and one GPIO interrupt.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The link support is no longer limited to the pseudo file system and now
covers both soft (symbolic) links and hard links across the VFS. Rename
the configuration option PSEUDOFS_SOFTLINKS to the more accurate FS_LINKS
and update all references in the source, headers, Kconfig, documentation
and board defconfigs accordingly.
This is a configuration rename; any out-of-tree defconfig that still
selects PSEUDOFS_SOFTLINKS must be updated to FS_LINKS.
Signed-off-by: zhengyu16 <zhengyu16@xiaomi.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8721F (amebagreen2). The driver is chip-agnostic and reads only
per-chip macros from ameba_rtc_chip.h; RTL8721F differs from amebadplus
only in the RTC interrupt vector (RTL8721F_IRQ_RTC, vector 41). The
APBPeriph_RTC masks and RTC_BASE_YEAR (1900) are identical across all
current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8721f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8720F. The driver is chip-agnostic and reads only per-chip macros
from ameba_rtc_chip.h; RTL8720F differs from amebadplus only in the RTC
interrupt vector (RTL8720F_IRQ_RTC, vector 33). The APBPeriph_RTC masks
and RTC_BASE_YEAR (1900) are identical across all current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8720f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Expose the Ameba on-chip RTC as a NuttX date/time RTC at /dev/rtc0
(rdtime/settime) with a single one-shot alarm (setalarm/rdalarm/
cancelalarm/setrelative) that fires the RTC interrupt and the upper-half
callback. The same hardware also backs the arch date/time RTC hooks
(up_rtc_initialize/getdatetime/settime, g_rtc_enabled) so the NuttX
system time is seeded from it.
The driver sits on the SDK fwlib RTC API (mirrored structures + local
externs, no vendor headers pulled into the NuttX include world). The
fwlib RTC API lives in the RAM source ameba_rtc.c, so it is added to the
board fwlib build under CONFIG_AMEBA_RTC. The hardware keeps a year plus
a day-of-year (no month/day register); the driver bridges that to the
NuttX month/day calendar with the libc UTC routines (timegm/gmtime_r),
which is exact and reversible.
The only per-chip fact -- the RTC interrupt vector -- lives in the
per-chip ameba_rtc_chip.h; the shared driver is never edited for a new
Ameba chip. A configs/rtc profile (examples/alarm) is added for
verification.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
