Describe the GPT timer support on the RA8M1 platform page and the
Arduino shield header's D2-D13 GPIO mapping on the EK-RA8M1 board page,
including the ek-ra8m1:timer-gpio configuration used to test them.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: leocafonso <leocafonso@gmail.com>
The SAADC internal sample timer only works with a single enabled
channel, so hardware-timed multi-channel scan was not possible. Add
NRF52_SAADC_TIMER_PPI, a third trigger mode in which a general-purpose
TIMER compare event is routed to TASKS_SAMPLE over PPI. All enabled
channels are scanned, and the TIMER prescaler allows much lower sample
rates than the internal timer, which is limited to 16MHz/CC with CC in
80..2047.
NRF52_SAADC_CONTINUOUS is no longer tied to the internal timer and
works with either source. Its EasyDMA buffers now hold
NRF52_SAADC_CONTINUOUS_BUFLEN whole scans rather than that many single
samples, so MAXCNT becomes chan_len * BUFLEN. Samples are interleaved
scan by scan, so a channel map is built once at configure() time and
passed to the upper half with the batch; the upper half already accepts
a per-sample channel array. A single-channel configuration produces
the same MAXCNT and the same delivery as before.
Because both features want a PPI channel, add a build-time check that
NRF52_SAADC_PPI_CHANNEL and NRF52_SAADC_CONTINUOUS_PPI_CH differ, and
constrain the latter under the SoftDevice controller like the former.
NRF52_SAADC_CHANNELS gains a default and range for the new mode, and
documents that the internal timer is restricted to one channel.
Assisted-by: Claude Code
Signed-off-by: raiden00pl <raiden00@railab.me>
Add a Features bullet and a "uart" configuration section to the
RTL8730E EVB board page describing UART0-2 as /dev/ttyS1-3 at
115200 8N1, the serialrx / serialblaster loopback examples and the
runtime TERMIOS support, following the pke8721daf board format.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
A MIMXRT1176 flight controller built to the Pixhawk FMUv6X-RT standard, so
the port also covers the NXP MR-VMU-RT1176.
Board data comes from PX4, which already carries it as a NuttX board config:
the clock tree, the LPUART1 pinmux, and the Macronix octal flash
configuration block the boot ROM reads at offset 0x400.
The board ships with the PX4 bootloader in the first 128 KB of QSPI, so the
image links at 0x30020000 and is loaded by it rather than written to the
flash base. The console is CDC/ACM as on teensy-4.x, so a USB cable is the
only thing needed to run NuttX here.
Signed-off-by: Royyan Zahir <royzah@gmail.com>
- Switch board image directive from .. image:: to .. figure:: with
:scale: 50 % and a caption line, matching the format used by other
Ameba board docs (rtl8721dx, rtl8721f).
- Move rtl8730e_evb.png from img/ subdirectory to the same level as
index.rst, consistent with other boards.
- Add gpio configuration section describing the three registered pins
(PB19 output /dev/gpio0, PB20 input /dev/gpio1, PB11 interrupt
/dev/gpio2), usage examples and pin encoding notes.
- Add GPIO to the "Supported in this NuttX port" feature list.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Record the vhost-net link in the board's Peripheral Support list and
describe the netnsh configuration alongside nsh, including how to bring
the interface up on both sides.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adopt the zbus message bus on the linum-stm32h753bi (first adopter
board):
- scripts/flash.ld: include the iterable sections common fragments
(2 lines: common-rom.ld inside .text, common-ram.ld inside .data).
- configs/zbus/defconfig: board configuration enabling zbus with all
observer types, the zbus example and its cmocka test suite
(./tools/configure.sh linum-stm32h753bi:zbus).
- Board documentation: describe the new configuration.
Validated on hardware: the 16-test cmocka suite passes twice in the
same boot and the zbus example produces the expected output.
Assisted-by: Claude Code
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Record the rptun/rpmsg link to the Linux A53 in the board's Peripheral
Support list.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
The STM32H7 page did not say anything about the Ethernet MAC.
- Describe the time counter of the MAC, the STM32_ETH_PTP option and its
behavior when the interface goes down.
- Describe the pulse-per-second output and the pins it can use.
- Describe the /dev/ptp0 clock the driver registers and the operations it
offers, and show a configuration that enables all of it.
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Assisted-by: Claude:claude-sonnet-5
The STM32F4 page did not say anything about the Ethernet MAC.
- Describe the time counter of the MAC and the options that enable the
timestamping of received packets, the pulse-per-second output and
the use of the counter as a high-resolution RTC.
- Describe the /dev/ptp0 clock that the driver registers: the
operations it offers, the numbering, and that the timestamps of the
received packets are values of the MAC counter and not of
CLOCK_REALTIME, so they have to be compared with /dev/ptp0.
- Show how to start ptpd with them and a configuration that enables
everything above.
- Say that the driver does not timestamp transmitted packets.
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Assisted-by: Claude:claude-sonnet-5
Add the documentation for the new supported board configurations and for the architecture,
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Record the eCAP1 and eCAP2 APWM outputs in the board's Peripheral
Support list.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Record the EPWM0 and EPWM1 outputs in the board's Peripheral Support
list.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Record the WKUP_I2C0 master in the board's Peripheral Support list.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Add a Peripheral Support section to the board page listing the GPIO and
MCU_MCSPI0 drivers, and replace the "UART console only" warning on both
the chip and board pages -- it no longer describes the port. The
replacement states what actually constrains the port: NuttX runs on the
R5F under RemoteProc and depends on the bootloader or Linux Device
Manager having powered and clocked the peripherals, because there is no
TISCI client yet.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
bitbucket.org/nuttx/buildroot returns 404, as does every other repository
under that Bitbucket organisation. The buildroot that still carries the
NuttX toolchain, ldnxflat included, is github.com/patacongo/buildroot.
Thirty three files carried the dead address, most of them as a "Bitbucket
download site" for a board's toolchain. There are no downloads to offer, so
those now name the repository, and the surrounding prose says so.
The other dead Bitbucket addresses are left alone: nuttx/nuttx, nuttx/tools,
nuttx/uclibc and nuttx/nxwidgets need a decision each about what replaces
them, which is not this patch. patacongo/obsoleted is still there.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Add a "fastboot_usb" section to the waveshare-rp2040-zero and
waveshare-rp2040-lcd-1.28 board doc pages, describing the USB fastboot
composite configuration added by the previous commits: fastbootd runs
on boot instead of NSH, composed together with CDC/ACM for the
console, and reachable on the host via fastboot devices/getvar/reboot.
Assisted-by: OpenCode:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba timer driver
(arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0
(TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC
masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two
32-bit basic LTIM timers at 0x40819200 / 0x40819400, 32.768 kHz,
APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h
/ sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build
hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in
by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up
registration and a timer defconfig. The shared driver is unchanged.
TIM0 is left untouched because the boot ROM claims it as the always-on
system timer; reprogramming it would break every SDK delay.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba timer driver
(arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0
(TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC
masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two
32-bit basic LTIM timers at 0x40808200 / 0x40808400, 32.768 kHz,
APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h
/ sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build
hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in
by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up
registration and a timer defconfig. The shared driver is unchanged.
TIM0 is left untouched because the boot ROM claims it as the always-on
system timer; reprogramming it would break every SDK delay.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a parameterised NuttX timer lower-half for the Realtek Ameba
general-purpose timers, sitting on the SDK fwlib RTIM register layer and
registered at /dev/timerN. The shared driver
(arch/arm/src/common/ameba/ameba_timer.c) reads a per-chip instance
table (ameba_timer_chip.h) for each timer's base, input clock, RCC gate
masks and IRQ; the period is programmed directly in microseconds and
converted to the 32-bit auto-reload with one clkfreq formula.
On the pke8721daf two of the 32.768 kHz "basic" (LTIM) timers are
exposed: /dev/timer0 is TIM1 and /dev/timer1 is TIM2. TIM0 is left
untouched because the boot ROM claims it as the always-on system timer
(SYSTIMER); reprogramming it would break every SDK delay. The RTIM
time-base entry points resolve to ROM, while the interrupt-clear and
period-change helpers come from the fwlib RAM source ameba_tim.c (shared
with the PWM driver).
Verified on hardware with examples/timer against both devices: the
update interrupt fires at the requested 1 s interval (measured with the
independent ROM SYSTIMER = 32768 ticks = 1.000 s).
Also whitelist the vendor RTIM_ symbol prefix in tools/nxstyle.c,
alongside the existing RCC_/SYSTIMER_ Ameba SDK entries.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Adopt the zbus message bus on the linum-stm32h753bi (first adopter
board):
- scripts/flash.ld: include the iterable sections common fragments
(2 lines: common-rom.ld inside .text, common-ram.ld inside .data).
- configs/zbus/defconfig: board configuration enabling zbus with all
observer types, the zbus example and its cmocka test suite
(./tools/configure.sh linum-stm32h753bi:zbus).
- Board documentation: describe the new configuration.
Validated on hardware: the 16-test cmocka suite passes twice in the
same boot and the zbus example produces the expected output.
Assisted-by: Claude Code
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x4080AD80,
CPU0_NS_WDG IRQ 69, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x40801D80,
KM4TZ_NS_WDG IRQ 52, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Also corrects the RTL8720F row in the rtl8721dx chip-header reference
table (the non-secure system WDG IRQ is KM4TZ_NS_WDG = 52).
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a NuttX watchdog lower-half for the Ameba KM4 non-secure system
watchdog (WDG2), registered as /dev/watchdog0. The fwlib WDG API is
ROM-resident, so no board.mk change is needed.
The hardware cannot be stopped once enabled, so stop() is emulated via
the early interrupt (EI) auto-refreshing the counter, and capture()
delivers a pre-timeout callback through the same EI. The EI has a
three-part timing contract, all handled here: it must be armed with
EIMOD=ENABLE at WDG_Init, its EIE gate only takes effect after
WDG_Enable, and -- because the EI is level-based -- a pure capture path
must mask EIE after the one-shot callback to avoid re-entrant storming
while the reset is pending. The EI flag is cleared twice per the slow
WDG clock.
Per-chip base address and IRQ live in ameba_wdg_chip.h so the shared
driver needs no change to port to another Ameba IC.
Verified on pke8721daf: timeout reset (BOOT REASON WDG2), stop()
suppressing the reset, and capture() firing ~EICNT ms before the reset.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8721F (amebagreen2). The driver is chip-agnostic and reads only
per-chip macros from ameba_rtc_chip.h; RTL8721F differs from amebadplus
only in the RTC interrupt vector (RTL8721F_IRQ_RTC, vector 41). The
APBPeriph_RTC masks and RTC_BASE_YEAR (1900) are identical across all
current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8721f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8720F. The driver is chip-agnostic and reads only per-chip macros
from ameba_rtc_chip.h; RTL8720F differs from amebadplus only in the RTC
interrupt vector (RTL8720F_IRQ_RTC, vector 33). The APBPeriph_RTC masks
and RTC_BASE_YEAR (1900) are identical across all current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8720f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Expose the Ameba on-chip RTC as a NuttX date/time RTC at /dev/rtc0
(rdtime/settime) with a single one-shot alarm (setalarm/rdalarm/
cancelalarm/setrelative) that fires the RTC interrupt and the upper-half
callback. The same hardware also backs the arch date/time RTC hooks
(up_rtc_initialize/getdatetime/settime, g_rtc_enabled) so the NuttX
system time is seeded from it.
The driver sits on the SDK fwlib RTC API (mirrored structures + local
externs, no vendor headers pulled into the NuttX include world). The
fwlib RTC API lives in the RAM source ameba_rtc.c, so it is added to the
board fwlib build under CONFIG_AMEBA_RTC. The hardware keeps a year plus
a day-of-year (no month/day register); the driver bridges that to the
NuttX month/day calendar with the libc UTC routines (timegm/gmtime_r),
which is exact and reversible.
The only per-chip fact -- the RTC interrupt vector -- lives in the
per-chip ameba_rtc_chip.h; the shared driver is never edited for a new
Ameba chip. A configs/rtc profile (examples/alarm) is added for
verification.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
List every peripheral implemented by STM32U3C5, and update the common GPIO, EXTI
and USART driver paths after the Cortex-M33 migration.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add HSI48 clock selection, USB pull-up control, automatic CDC/ACM registration during board bring-up, USB test configurations, and board documentation.
Assisted-by: OpenAI Codex
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Wire the shared Ameba ADC driver into the RTL8721F build: add the
per-chip ameba_adc_chip.h (12 channels, CH0..CH7 external on
PA20,PA19,PA18,PA17,PA15,PA14,PA13,PA12, PINMUX function 5), the
board ADC table and registration, the adc board config, and build
glue for both cmake and make (including the fwlib RAM-layer
ameba_adc.c in ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba ADC driver into the RTL8720F build: add the
per-chip ameba_adc_chip.h (9 channels, CH0..CH5 external on
PA13..PA18, PINMUX function 5, APB clock on bit24), the board ADC
table and registration, the adc board config, and build glue for
both cmake and make (including the fwlib RAM-layer ameba_adc.c in
ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Add a NuttX ADC lower-half for the Ameba SoC family, wired for the
amebadplus/pke8721daf as /dev/adc0. The driver uses the fwlib ROM
API and drives on-demand polled conversions via ADC_ReceiveBuf with
the hardware auto channel-switch FIFO, because amebadplus disables the
ADC software-trigger path. Per-chip wiring (channel count, pinmux
function id, APB clock bits, optional aux clock) lives in a chip
header so a new IC only supplies its own values without touching the
shared driver.
Reports raw conversion codes per the NuttX convention (12-bit
effective, 0..~3876 for 0..3.3V), consistent with the STM32/i.MXRT/
Tiva ADC drivers.
Verified on hardware: 0V->121, 3.3V->3876 on CH0(PB19) while
CH1(PB18) held steady, confirming sampling, full-scale and
multi-channel switch-list isolation.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
