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!arch/stm32: move stm32l1 and finalize the directory split

Browse source 
Move the stm32l1 sources, headers and boards into arch/arm/src/stm32l1,
arch/arm/include/stm32l1 and boards/arm/stm32l1, then finalize the split:
source each split family directly in arch/arm/Kconfig and boards/Kconfig and
remove the now-empty combined arch/arm/src/stm32 and boards/arm/stm32 trees.

BREAKING CHANGE: The legacy STM32 architecture and board paths were split into
stm32f1, stm32l1, stm32f2, stm32f3, stm32f4, and stm32g4 directories.
Out-of-tree boards must move from stm32 to the matching split family.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-25 22:44:13 +02:00 • committed by Xiang Xiao
parent 62b0dbe851
commit db5afb356e
175 changed files with 3328 additions and 11152 deletions
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2
Documentation/applications/examples/ft80x/index.rst
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@ -4,4 +4,4 @@
This examples has ports of several FTDI demos for the FTDI/BridgeTek FT80x GUI
chip. As an example configuration, see
``nuttx/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig``.
``nuttx/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig``.

2
Documentation/applications/system/usbmsc/index.rst
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@ -13,7 +13,7 @@ This function will be called by the ``system/usbmsc`` indirectly via the ``board
block device drivers. For examples of the implementation of
``board_usbmsc_initialize()`` see
``boards/arm/lpc214x/mcu123-lpc214x/src/up_usbmsc.c`` or
``boards/arm/stm32/stm3210e-eval/src/usbmsc.c``.
``boards/arm/stm32f1/stm3210e-eval/src/usbmsc.c``.
Configuration options:

2
Documentation/components/drivers/character/leds/userled.rst
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@ -59,7 +59,7 @@ Files supporting USERLED can be found in the following locations:
Something important to note is that your board initialization code (normally named ``<arch>_bringup.c`` should call the function to register the driver.
For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem:
For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem:
.. code-block:: C

2
Documentation/components/drivers/character/serial.rst
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@ -39,7 +39,7 @@ Serial Device Drivers
`character drivers <#chardrivers>`__ and are accessed as other
character drivers.
- **Examples**: ``arch/arm/src/stm32/stm32_serial.c``,
- **Examples**: ``arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c``,
``arch/arm/src/lpc214x/lpc214x_serial.c``,
``arch/z16/src/z16f/z16f_serial.c``, etc.

6
Documentation/components/drivers/special/lcd.rst
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@ -85,7 +85,7 @@ LCDs
Generic LCD driver for LCDs based on the Solomon Systech
SSD1289 LCD controller. Think of this as a template for an LCD driver
that you will probably have to customize for any particular LCD
hardware. (See also boards/arm/stm32/hymini-stm32v/src/ssd1289.c below).
hardware. (See also boards/arm/stm32f1/hymini-stm32v/src/ssd1289.c below).
- ``st7567.c``
@ -120,7 +120,7 @@ OLEDs
OLED Display Module, UUG-2864AMBAG01, Univision Technology Inc.
Based on the SH1101A controller. Example usage::
boards/arm/stm32/stm32f4discovery
boards/arm/stm32f4/stm32f4discovery
boards/arm/lpc214x/zp214xpa
- ``ug-9664hswag01.c``
@ -140,7 +140,7 @@ OLEDs
Densitron Technologies DD-12864WO-4A which is based on SSD1309 LCD
controller. Example usage::
boards/arm/stm32/stm32f4discovery
boards/arm/stm32f4/stm32f4discovery
boards/arm/sam34/sam4l-xplained
Segment LCDS (SLCDs)

2
Documentation/components/drivers/special/sdio.rst
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@ -29,7 +29,7 @@ SDIO Device Drivers
#. Provide that instance to the initialization method of the
higher level device driver.
- **Examples**: ``arch/arm/src/stm32/stm32_sdio.c`` and
- **Examples**: ``arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c`` and
``drivers/mmcsd/mmcsd_sdio.c``
Implementing an SDIO lower-half

2
Documentation/components/drivers/special/usbdev.rst
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@ -19,7 +19,7 @@ USB Device-Side Drivers
``arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c``,
``arch/arm/src/lpc214x/lpc214x_usbdev.c``,
``arch/arm/src/lpc313x/lpc313x_usbdev.c``, and
``arch/arm/src/stm32/stm32_usbdev.c``.
``arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c``.
- ``struct usbdevclass_driver_s``. Each USB device class
driver must implement an instance of

2
Documentation/components/drivers/special/usbhost.rst
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@ -17,7 +17,7 @@ USB Host-Side Drivers
**Examples**: ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c``,
``arch/arm/src/stm32/stm32_otgfshost.c``,
``arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c``,
``arch/arm/src/sama5/sam_ohci.c``, and
``arch/arm/src/sama5/sam_ehci.c``.

2
Documentation/contributing/making-changes.rst
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@ -227,7 +227,7 @@ squash before submitting the Pull Request:
.. code-block:: bash
arch/arm/stm32/: Add arch support for stm32 platform
arch/arm/stm32f4/: Add arch support for stm32f4 platform
This patch adds initial support for stm32 platform. Please read
the documentation included for more details how to wire the display.

4
Documentation/guides/changing_systemclockconfig.rst
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@ -28,7 +28,7 @@ Custom Clock Configuration
The ``configs/vsn/`` configuration does something like you say. It skips the
initial clock configuration by defining
``CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y``. Then the normal clock
configuration logic in ``arch/arm/src/stm32/stm32_rcc.c`` is not executed.
configuration logic in ``arch/arm/src/stm32f4/stm32_rcc.c`` is not executed.
Instead, the "custom" clock initialization at ``configs/vsn/src/sysclock.c``
is called:
@ -83,7 +83,7 @@ are hardcoded in the board.h header file. So you have two options:
2. **Variable Peripheral Clocking**. You can make the peripheral clocking
variable. I had to do this for the SAMA5Dx family. Look at
``boards/arm/stm32/sama5d4-ek/include/board_sdram.h`` for example. Notice
``boards/arm/sama5/sama5d4-ek/include/board_sdram.h`` for example. Notice
that the frequencies are not constants, but function calls:
.. code-block:: c

2
Documentation/guides/etcromfs.rst
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@ -86,7 +86,7 @@ behave as follows at Nuttx start-up time:
``CONFIG_ETC_ROMFS=y`` in the NuttX configuration file. They might
provide useful examples:
- ``boards/arm/stm32/hymini-stm32v/nsh2``
- ``boards/arm/stm32f1/hymini-stm32v/nsh2``
- ``boards/arm/dm320/ntosd-dm320/nsh``
- ``boards/sim/sim/sim/nsh``
- ``boards/sim/sim/sim/nsh2``

4
Documentation/guides/ipv6.rst
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@ -218,7 +218,7 @@ Board Configurations
At present, there are three board configuration that are pre-configured to
use IPv6: ``nuttx/boards/arm/tiva/dk-tm4c129x/configs/ipv6``,
``nuttx/boards/arm/stm32/stm32f4discovery/ipv6``, and
``nuttx/boards/arm/stm32f4/stm32f4discovery/ipv6``, and
``nuttx/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6``. These default
configurations have only IPv6 enabled. But the `README` files at in those
board directories describes how to enable `both` IPv4 and IPv6 simultaneously.
@ -345,4 +345,4 @@ the network utils (``netutils``).
* Netutils: The network utilities in ``apps/netutils`` have been adapted to
work with IPv6: DHCP, FTP, TFTP, Telnet, etc. Support for managing IPv6
address have been included in the ``netlib``, but nothing else has yet been
updated.
updated.

2
Documentation/guides/nsh_network_link_management.rst
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@ -45,7 +45,7 @@ must be satisfied:
are implemented for Atmel SAM4/4, SAMA5 families, and for the STMicro STM32.
See ``nuttx/arch/arm/src/sam34/sam_emac.c``,
``nuttx/arch/arm/src/sam34/sam_emaca.c``, ``sam_emacb.c``, and ``sam_gmac.c``,
and ``nuttx/arch/arm/src/stm32/stm32_eth.c``.
and ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``.
- ``CONFIG_ARCH_PHY_INTERRUPT``
This is not a user-selectable option. Rather, it is set when selecting a board
that supports PHY interrupts. In most architectures, the PHY interrupt is not

2
Documentation/guides/ofloader.rst
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@ -52,7 +52,7 @@ Precautions
1.If you need to implement the ofloader on a different board,
you will need to read the `wiki <https://wiki.segger.com/SEGGER_Flash_Loader>`
and refer to the implementation of "ofloader.ld" linker script located
in the "boards/arm/stm32/stm32f429i-disco/scripts" directory.
in the "boards/arm/stm32f4/stm32f429i-disco/scripts" directory.
This linker script defines how the different sections of the NuttX image are placed in memory.
You should configure the corresponding sections to be located in RAM,
where the J-Link can write the image correctly.

2
Documentation/guides/partially_linked_elf.rst
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@ -40,7 +40,7 @@ compatible with the example provided here:
In this example, let's illustrate this using an STM32F4-Discovery
configuration. We will assume that you have modified the
``boards/arm/stm32/stm32fdiscovery/src/stm32_bringup.c`` file, adding the
``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` file, adding the
following:
.. code-block:: c

2
Documentation/guides/port_drivers_to_stm32f7.rst
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@ -191,7 +191,7 @@ An Example
There is a good example in the STM32 Ethernet driver. The STM32 F7
Ethernet driver (``arch/arm/src/stm32f7/stm32_ethernet.c``) derives
directly from the STM32 F4 Ethernet driver
(``arch/arm/src/stm32/stm32_eth.c``). These two Ethernet MAC peripherals
(``arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``). These two Ethernet MAC peripherals
are nearly identical. Only changes that are a direct consequence of the
STM32 F7 D-Cache were required to make the driver work on the STM32 F7.
Those changes are summarized below.

22
Documentation/guides/protected_build.rst
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@ -177,10 +177,10 @@ Files and Directories
Here is a summary of directories and files used by the STM32F4Discovery
protected build:
* ``boards/arm/stm32/stm32f4discovery/configs/kostest``. This is the kernel
* ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. This is the kernel
mode OS test configuration. The two standard configuration files
can be found in this directory: (1) ``defconfig`` and (2) ``Make.defs``.
* ``boards/arm/stm32/stm32f4discovery/kernel``. This is the first past
* ``boards/arm/stm32f4/stm32f4discovery/kernel``. This is the first past
build directory. The Makefile in this directory is invoked to
produce the pass1 object (``nuttx_user.elf`` in this case). The
second pass object is created by ``arch/arm/src/Makefile``. Also
@ -188,7 +188,7 @@ protected build:
contains a header that includes information need by the kernel
blob in order to interface with the user-code. That header is
defined in by this file.
* ``boards/arm/stm32/stm32f4discovery/scripts``. Linker scripts for
* ``boards/arm/stm32f4/stm32f4discovery/scripts``. Linker scripts for
the kernel mode build are found in this directory. This includes
(1) ``memory.ld`` which hold the common memory map, (2) ``user-space.ld``
that is used for linking the pass1 user-mode blob, and (3)
@ -314,11 +314,11 @@ Comparing the "Flat" Build Configuration with the Protected Build Configuration
===============================================================================
Compare, for example the configuration
``boards/arm/stm32/stm32f4discovery/configs/ostest`` and the
configuration ``boards/arm/stm32/stm32f4discovery/configs/kostest``.
``boards/arm/stm32f4/stm32f4discovery/configs/ostest`` and the
configuration ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``.
These two configurations are identical except that one builds a
"flat" version of OS test and the other builds a kernel version
of the OS test. See the file ``boards/arm/stm32/stm32f4discovery/README.txt``
of the OS test. See the file ``boards/arm/stm32f4/stm32f4discovery/README.txt``
for more details about those configurations.
The configurations can be compared using the ``cmpconfig`` tool:
@ -328,7 +328,7 @@ The configurations can be compared using the ``cmpconfig`` tool:
cd tools
make -f Makefile.host cmpconfig
cd ..
tools/cmpconfig boards/arm/stm32/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig
tools/cmpconfig boards/arm/stm32f4/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig
Here is a summary of the meaning of all of the important differences in the
configurations. This should be enough information for you to convert any
@ -337,7 +337,7 @@ configuration from a "flat" to a protected build:
* ``CONFIG_BUILD_2PASS=y``. This enables the two pass build.
* ``CONFIG_BUILD_PROTECTED=y``. This option enables the "two pass"
protected build.
* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel"``.
* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel"``.
This tells the build system the (relative) location of the pass1 build directory.
* ``CONFIG_PASS1_OBJECT=""``. In some "two pass" build configurations,
the build system need to know the name of the first pass object.
@ -382,7 +382,7 @@ configuration from a "flat" to a protected build:
These includes such things as initializing device drivers.
These same initialization steps must be performed in kernel
mode for the protected build and ``CONFIG_BOARD_LATE_INITIALIZE``.
See ``boards/arm/stm32/stm32f4discovery/src/up_boot.c`` for an
See ``boards/arm/stm32f4/stm32f4discovery/src/up_boot.c`` for an
example of such board initialization code.
Architecture-Specific Options:
@ -409,8 +409,8 @@ Size Expansion
The protected build will, or course, result in a FLASH image that is
larger than that of the corresponding "flat" build. How much larger?
I don't have the numbers in hand, but you can build
``boards/arm/stm32/stm32f4discovery/configs/nsh`` and
``boards/arm/stm32/stm32f4discovery/configs/kostest`` and compare
``boards/arm/stm32f4/stm32f4discovery/configs/nsh`` and
``boards/arm/stm32f4/stm32f4discovery/configs/kostest`` and compare
the resulting binaries for yourself using the ``size`` command.
Increases in size are expected because:

10
Documentation/guides/smaller_vector_tables.rst
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@ -202,7 +202,7 @@ Most ARMv7-M architectures support two mechanism for handling interrupts:
``CONFIG_ARMV7M_CMNVECTOR=y`` that can be found in
``arch/arm/src/armv7-m/``, and
* MCU-specific interrupt handling logic. For the
STM32, this logic can be found at ``arch/arm/src/stm32/gnu/stm32_vectors.S``.
STM32, this logic can be found at ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``.
The `common` vector logic is slightly more efficient,
the MCU-specific logic is slightly more flexible.
@ -229,7 +229,7 @@ This technical approach requires changes to three files:
define ``only`` the small set of 20 ``mapped`` IRQ numbers in
the range from 0 through 19. It would also set ``NR_IRQS``
to the value 20.
* A new header file at ``arch/arm/src/stm32/hardware``, say
* A new header file at ``arch/arm/src/stm32f4/hardware``, say
``xyz_vector.h``. It would be similar to the other vector
definitions files in that directory: It will consist
of a sequence of 100 ``VECTOR`` and ``UNUSED`` macros. It will
@ -248,7 +248,7 @@ This has all been replaced with the common vector handling at
Vector Definitions
==================
In ``arch/arm/src/stm32/gnu/stm32_vector.S``, notice that the
In ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``, notice that the
``xyz_vector.h`` file will be included twice. Before each
inclusion, the macros ``VECTOR`` and ``UNUSED`` are defined.
@ -290,7 +290,7 @@ file like this:
...
Where the value of ``STM32_IRQ_USART1`` was defined to
be 12 in the ``arch/arm/include/stm32/xyz_irq.h`` header
be 12 in the ``arch/arm/include/stm32f4/xyz_irq.h`` header
file. When ``xyz_vector.h`` is included by ``stm32_vectors.S``
with the above definitions for ``VECTOR`` and ``UNUSED``, the
following would result:
@ -349,7 +349,7 @@ second time the ``xzy_vector.h`` is included by ``stm32_vectors.S``:
In the above USART1 example, a single handler would be
generated that will provide the IRQ number 12. Remember
that 12 is the expansion of the macro ``STM32_IRQ_USART1``
that is provided in the ``arch/arm/include/stm32/xyz_irq.h``
that is provided in the ``arch/arm/include/stm32f4/xyz_irq.h``
header file:
.. code-block:: asm

2
Documentation/guides/stm32ccm.rst
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@ -34,7 +34,7 @@ This memory allocator is automatically enabled when the following options are se
* ``CONFIG_MM_MULTIHEAP`` Support for multiple heaps is enabled.
Under those conditions, the CCM memory allocator is enabled and the allocator
interfaces prototyped in the ``arch/arm/src/stm32/stm32_ccm.h`` are available.
interfaces prototyped in the ``arch/arm/src/common/stm32/stm32_ccm.h`` are available.
NOTE: These interfaces are, technically, not prototyped since they are really
provided via C pre-processor macros.

2
Documentation/guides/usingkernelthreads.rst
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@ -52,7 +52,7 @@ In order to build the task into the OS as a kernel thread, you simply have to:
(1) place the kernel thread code in your board source code directory, and (2)
start it with ``kthread_create()`` in your board bring-up logic. There a few
examples of this in the NuttX source tree. Here is one:
`https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c <https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c>`_
`https://github.com/apache/nuttx/blob/master/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c <https://github.com/apache/nuttx/blob/master/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c>`_
So that is another trick that you can use to architecture optimal solutions:
Create parts of your applications as kernel threads: They need to reside in

4
Documentation/guides/zerolatencyinterrupts.rst
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@ -302,8 +302,8 @@ You can find an example that tests the high priority, nested interrupts in the N
* :doc:`/platforms/arm/stm32f1/boards/viewtool-stm32f107/index` Description of
the configuration
* ``nuttx/boards/arm/stm32/viewtool-stm32f107/highpri`` Test configuration
* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/highpri`` Test configuration
* ``nuttx/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri`` Test
* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri`` Test
driver.

10
Documentation/implementation/chip_h.rst
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@ -12,16 +12,16 @@ If you wonder about the purpose of the two ``chip.h`` files in each arm chip.
.. code:: sh
$ find arch/arm -name chip.h | grep stm32
arch/arm/include/stm32/chip.h
arch/arm/src/stm32/chip.h
arch/arm/include/stm32f4/chip.h
arch/arm/src/stm32f4/chip.h
The reason behind ``arch/arm/src/stm32/chip.h`` file was a bad idea
The reason behind ``arch/arm/src/stm32f4/chip.h`` file was a bad idea
that happened a long time ago.
Right now, I believe that its only required when ``CONFIG_ARMV7M_CMNVECTOR``
is selected in the configuration. In that case, ``arch/arm/src/stm32/chip.h``
is selected in the configuration. In that case, ``arch/arm/src/stm32f4/chip.h``
is included by ``arch/arm/src/armv7-m/up_vectors.c`` in order provide
the number of interrupt vectors. In stm32, ``arch/arm/src/stm32/chip.h``
the number of interrupt vectors. In stm32, ``arch/arm/src/stm32f4/chip.h``
provides the number of vectors indirectly by including the correct,
chip-specific vectors.h file.
This function is a little more obvious in ``arch/arm/srch/lpc43xx/chip.h``.

8
Documentation/implementation/file_descriptors.rst
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@ -135,7 +135,7 @@ Detached File Helpers
Once the file structure has been detached from its file descriptor,
you can no longer use the standard VFS functions ``read()``, ``write()``,
``ioctl()``, etc. Fortunately, there are a parallel set of interfaces
that can be used with detached files. These are decribed in detail
that can be used with detached files. These are described in detail
in ``include/nuttx/fs/fs.h`` and only listed here below:
.. code-block:: c
@ -153,8 +153,8 @@ in ``include/nuttx/fs/fs.h`` and only listed here below:
int file_vfcntl(FAR struct file *filep, int cmd, va_list ap);
The SYLOG Device: A Case Study
==============================
The SYSLOG Device: A Case Study
===============================
This technique is used for the SYSLOG device. Originally, NuttX used
file descriptor ``1`` for SYSLOG output by default. For most task groups,
@ -179,7 +179,7 @@ Other Examples
There are some other examples in analog joystick lower half drivers
that use the ADC character driver to read joystick positions::
boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c:
boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c:
ret = file_detach(fd, &g_adcfile);
boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c:

26
Documentation/implementation/nuttx_initialization_sequence.rst
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@ -35,7 +35,7 @@ to any supported architecture.
Here is the map of initialization function calls::
__start()-arch/arm/src/stm32/stm32_start.c
__start()-arch/arm/src/common/stm32/stm32_start_m3m4_v1.c
|
+--*Set stack limit
+--stm32_clockconfig()
@ -45,7 +45,7 @@ Here is the map of initialization function calls::
+--showprogress('A')
+--
+--
+--stm32_boardinitialize()-boards/arm/stm32/stm32f4discovery/src/stm32_boot.c
+--stm32_boardinitialize()-boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c
| |
| +--stm32_spidev_initialize()-stm32_spi.c:ONLY CHIP SELECTS
| +--stm32_usbinitialize()-
@ -196,7 +196,7 @@ There are few important things to note about this file.
``.section .vectors, ax``. This pseudo operation will place all of the
vectors into a special section call ``.vectors``.
On of the STM32 F4 linker scripts is located at
``nuttx/boards/arm/stm32/stm32f4discovery/scripts/ld.script``.
``nuttx/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script``.
In that file, you can see that section ``.vectors`` is forced to lie
at the very beginning of FLASH memory.
The STM32 F4 can be configured to boot in different ways via strapping.
@ -229,7 +229,7 @@ nuttx/arch/arm/src/stm32_start.c
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The reset vector ``__start`` lies in the file
``nuttx/arch/arm/src/stm32/stm32_start.c`` and does the real,
``nuttx/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c`` and does the real,
low-level architecture-specific initialization. This initialization includes:
1. ``stm32_clockconfig()`` - Initialize the PLLs and peripheral clocking
@ -262,7 +262,7 @@ low-level architecture-specific initialization. This initialization includes:
7. ``stm32_boardinitialize()`` - Board-specific logic is initialized by
calling this function. For the case of the STM32F4Discovery board,
this logic can be found at
``nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c`` and does
``nuttx/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c`` and does
the following operations:
a. ``stm32_spidev_initialize()`` - Initialize SPI chip selects
@ -351,19 +351,19 @@ file and in that case those operations are not performed:
``nx_start()``. However, if the board supports multiple, discontiguous
memory regions, any addition memory regions can be added to the heap
by this function. For the STM32 F4, ``up_addregion()`` is implemented
in ``nuttx/arch/arm/src/stm32/stm32_allocateheap.c``.
in ``nuttx/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c``.
* ``arm_pminitialize()`` - If ``CONFIG_PM`` is defined, the function must
initialize the power management subsystem. This MCU-specific function
must be called very early in the intialization sequence before any other
must be called very early in the initialization sequence before any other
device drivers are initialized (since they may attempt to register with
the power management subsystem). There is no implementation
of ``up_pminitialize()`` for any STM32 platform.
* ``arm_dmainitialize()`` - Initialize the DMA subsystem.
For the STM32 F4, this DMA initialization can be found in
``nuttx/arch/arm/src/stm32/stm32_dma.c`` (which includes
``nuttx/arch/arm/src/stm32f4xxx_dma.c``).
``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c`` (which includes
``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c``).
* ``devnull_register()`` - Registers the standard ``/dev/null``.
@ -381,11 +381,11 @@ file and in that case those operations are not performed:
(found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c`` STM32 F4).
* ``arm_netinitialize()`` - Initialize the network. For the STM32 F4,
this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``.
this function is in ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``.
* ``arm_usbinitialize()`` - Initialize USB (host or device).
For the STM32 F4, this function is in
``nuttx/arch/arm/src/stm32/stm32_otgfsdev.c``.
``nuttx/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c``.
* ``arm_l2ccinitialize()`` - Initialize the L2 cache if present
and selected.
@ -448,7 +448,7 @@ This function performed the following specific operations:
for a variety of purposes like misc garbage clean-up.
* ``nx_create_initthread()`` - Once the operating system has been initialized,
this funcions either directly calls ``nx_start_application()`` or creates
this functions either directly calls ``nx_start_application()`` or creates
a thread for running it
* ``nx_start_application()`` - If set in the NuttX configuration,
@ -640,7 +640,7 @@ The resulting ROMFS file system can be found in
* ``board_app_initialize()`` - For the STM32F4Discovery, this architecture
specific initialization can be found at
``boards/arm/stm32/stm32f4discovery/src/stm32_appinit.c``.
``boards/arm/stm32f4/stm32f4discovery/src/stm32_appinit.c``.
This it does things like:
1. Initialize SPI devices.

4
Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst
View file

@ -228,13 +228,13 @@ OpenOCD
=======
I have also used OpenOCD with the M3 Wildfire. In this case, I used
the Olimex USB ARM OCD. See the script in boards/arm/stm32/fire-stm32v2/tools/oocd.sh
the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh
for more information. Using the script:
- Start the OpenOCD GDB server::
cd <nuttx-build-directory>
boards/arm/stm32/fire-stm32v2/tools/oocd.sh $PWD
boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh $PWD
- Load NuttX::

2
Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst
View file

@ -517,7 +517,7 @@ NOTES:
ADC_IN8 (PB0) CON5 CN14 Pin2
ADC_IN9 (PB1) CON5 CN14 Pin1
The signal selection is hard-coded in boards/arm/stm32/shenzhou/src/up_adc.c: The
The signal selection is hard-coded in boards/arm/stm32f1/shenzhou/src/up_adc.c: The
potentiometer input (only) is selected.
These selections will enable sampling the potentiometer input at 100Hz using

12
Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst
View file

@ -87,13 +87,13 @@ OpenOCD
=======
I have also used OpenOCD with the STM3210E-EVAL. In this case, I used
the Olimex USB ARM OCD. See the script in boards/arm/stm32/stm3210e-eval/tools/oocd.sh
the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh
for more information. Using the script:
- Start the OpenOCD GDB server::
cd <nuttx-build-directory>
boards/arm/stm32/stm3210e-eval/tools/oocd.sh $PWD
boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh $PWD
- Load NuttX::
@ -171,7 +171,7 @@ More complex temperature sensor operations are also available. See the
IOCTL commands enumerated in include/nuttx/sensors/lm75.h. Also read the
descriptions of the stm32_lm75initialize() and stm32_lm75attach()
interfaces in the arch/board/board.h file (sames as
boards/arm/stm32/stm3210e-eval/include/board.h).
boards/arm/stm32f1/stm3210e-eval/include/board.h).
NSH Command Line Application
----------------------------
@ -812,7 +812,7 @@ NOTES:
CONFIG_ARCH_CUSTOM_PMINIT=y
CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from
arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c.
arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c.
This allows us to support board-specific PM initialization.::
CONFIG_ARCH_IDLE_CUSTOM=y
@ -824,8 +824,8 @@ NOTES:
management.
The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the
normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace
this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c).
normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace
this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c).
4. Here are some additional things to note in the configuration::

4
Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst
View file

@ -186,7 +186,7 @@ instead of 64KiB as documented in the datasheet and reported by its internal
register.
In order to enable 128KiB you need modify the linker script to reflect this
new size. Open the boards/arm/stm32/stm32f103-minimum/scripts/ld.script and replace::
new size. Open the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script and replace::
flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K
@ -358,7 +358,7 @@ enable/disable these options using "make menuconfig" ::
Memory Management --->
[*] Small memory model
Also change the boards/arm/stm32/stm32f103-minimum/scripts/ld.script file to use 128KB
Also change the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script file to use 128KB
of Flash instead 64KB (since this board has a hidden 64KB flash) :
MEMORY

2
Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst
View file

@ -12,7 +12,7 @@ LEDs
It is assumed that STMicro STM32F100RB generic board board has one LED on PA0.
You should configure the port and pin number in
boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by
boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by
the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by
the board port is defined in include/board.h and src/up_leds.c. The LED is used
to encode OS-related events as follows::

2
Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst
View file

@ -79,7 +79,7 @@ Using JTAG
The Clicker2 comes with the mikroBootloader installed. That bootloader
has not been used and is possibly incompatible with the Clicker2-STM32
linker script at boards/arm/stm32/clicker2-stm32/scripts/flash.ld. Often code must
linker script at boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld. Often code must
be built to execute at an offset in to FLASH when a bootloader is used.
Certainly that is the case for the ST-Micro DFU bootloader but I am not
aware of the requirements for use with the mikroBootloader.

2
Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst
View file

@ -79,6 +79,6 @@ package as flexible as, say, an STM32F4 Discovery board.
Build Instructions
==================
The boards/arm/stm32/omnibusf4/nsh/defconfig file creates a basic setup, and
The boards/arm/stm32f4/omnibusf4/nsh/defconfig file creates a basic setup, and
includes drivers for all supported onboard chips. The console and
command prompt are sent to USART3.

14
Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst
View file

@ -517,7 +517,7 @@ MAPPING TO STM32 F4::
4 Also the reset pin for the CS43L22 audio Codec.
NOTE: The configuration to test this LCD configuration is available at
boards/arm/stm32/stm32f4discovery/nxlines. As of this writing, I have not seen the
boards/arm/stm32f4/stm32f4discovery/nxlines. As of this writing, I have not seen the
LCD working so I probably have some things wrong.
I might need to use a bit-banging interface. Below is the pin configuration
@ -613,7 +613,7 @@ that I am using::
Darcy Gong recently added support for the UG-2864HSWEG01 OLED which is also
an option with this configuration. I have little technical information about
the UG-2864HSWEG01 interface (see boards/arm/stm32/stm32f4discovery/src/up_ug2864hsweg01.c).
the UG-2864HSWEG01 interface (see boards/arm/stm32f4/stm32f4discovery/src/up_ug2864hsweg01.c).
NiceRF LoRa (2AD66-LoRa V2)
===========================
@ -639,7 +639,7 @@ connect the CS to PA4, connect RST to PE1 and finally connect INT to PE4.
The next step is to enable the ENC28J60 in the menuconfig ("make menuconfig")
and the necessary Network configuration, you can use the
boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig as reference.
boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig as reference.
HCI UART
========
@ -1202,7 +1202,7 @@ NOTES:
The HCI UART selection can be changed by re-configuring and assigning
the different U[S]ART to the HCI. The U[S]ART pin selections can be
changed by modifying the disambiguation definitions in
boards/arm/stm32/stm32f4discovery/include/board.h
boards/arm/stm32f4/stm32f4discovery/include/board.h
I have been testing with the DVK_BT960_SA board via J10 as follows::
@ -2021,7 +2021,7 @@ NOTES:
CONFIG_ARCH_CUSTOM_PMINIT=y
CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from
arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c.
arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c.
This allows us to support board-specific PM initialization.::
CONFIG_ARCH_IDLE_CUSTOM=y
@ -2033,8 +2033,8 @@ NOTES:
management.
The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the
normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace
this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c).
normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace
this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c).
3. Here are some additional things to note in the configuration::

2
Documentation/platforms/arm/stm32f4/index.rst
View file

@ -389,7 +389,7 @@ Here are a few tips before you start that effort:
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX
is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX
one time from the Cygwin command line in order to obtain the pre-built
startup object needed by RIDE.

2
Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst
View file

@ -106,7 +106,7 @@ Here are a few tips before you start that effort:
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX
is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX
one time from the Cygwin command line in order to obtain the pre-built
startup object needed by RIDE.

2
Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst
View file

@ -107,7 +107,7 @@ Here are a few tips before you start that effort:
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX
is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX
one time from the Cygwin command line in order to obtain the pre-built
startup object needed by RIDE.

2
Documentation/quickstart/organization.rst
View file

@ -68,7 +68,7 @@ specified by several settings in the NuttX configuration file.
sub-directories and are discussed in a paragraph
`below <#boards-subdirectory-structure>`__.
The directory ``boards/arm/stm32/stm32f4disovery/``, as an
The directory ``boards/arm/stm32f4/stm32f4discovery/``, as an
example, holds board-specific logic for the STM32F4 Discovery
board and is selected via the
``CONFIG_ARCH_BOARD="stm32f4discovery"`` configuration setting.

44
LICENSE
View file

@ -2918,7 +2918,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
boards/arm/stm32/photon/src/stm32_wlan_firmware.c
boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c
drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h
================================================
@ -3249,8 +3249,8 @@ ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
boards/arm/rp2040/common/src/rp2040_ina219.c
boards/arm/stm32/common/src/stm32_ina219.c
boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c
boards/arm/common/stm32/src/stm32_ina219.c
boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c
===============================================
Copyright (C) 2018,2019 Erle Robotics (Juan Flores Muñoz).
All rights reserved.
@ -3282,9 +3282,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
boards/arm/stm32/nucleo-f303re/src/stm32_uid.c
boards/arm/stm32/omnibusf4/src/stm32_uid.c
boards/arm/stm32/stm32f4discovery/src/stm32_uid.c
boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c
boards/arm/stm32f4/omnibusf4/src/stm32_uid.c
boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c
boards/arm/stm32h7/nucleo-h743zi/src/stm32_uid.c
boards/arm/stm32h7/stm32h747i-disco/src/stm32_uid.c
===============================================
@ -3317,8 +3317,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c
boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c
boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c
boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c
=================================================
Copyright (C) 2017 Gregory Nutt. All rights reserved.
Copyright (C) 2017 Brian Webb. All rights reserved.
@ -3350,10 +3350,10 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
boards/arm/stm32/omnibusf4/src/stm32_romfs.h
boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c
boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h
boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c
boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h
boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c
boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h
boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c
boards/arm/stm32f7/common/include/stm32_romfs.h
boards/arm/stm32f7/common/src/stm32_romfs_initialize.c
=============================================================
@ -3975,7 +3975,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/hardware/stm32f100_pinmap.h
arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h
=================================================
Copyright (C) 2009 Gregory Nutt. All rights reserved.
@ -4009,7 +4009,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h
arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h
====================================================
Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
@ -4042,7 +4042,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/stm32_i2c_alt.c
arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c
===================================
Copyright (C) 2011 Uros Platise. All rights reserved.
@ -4076,7 +4076,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/stm32_i2c_v2.c
arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c
===========================================
Copyright (C) 2011 Uros Platise. All rights reserved.
@ -4110,8 +4110,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/stm32_sdadc.c
arch/arm/src/stm32/stm32_sdadc.h
arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c
arch/arm/src/common/stm32/stm32_sdadc.h
===================================
Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved.
@ -4144,7 +4144,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/stm32_tickless.c
arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c
======================================
Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
@ -4177,7 +4177,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/stm32_tim_lowerhalf.c
arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c
===========================================
Copyright (C) 2015 Wail Khemir. All rights reserved.
@ -4210,8 +4210,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
arch/arm/src/stm32/stm32_uid.c
arch/arm/src/stm32/stm32_uid.h
arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c
arch/arm/src/common/stm32/stm32_uid.h
===================================
Copyright (C) 2015 Marawan Ragab. All rights reserved.

44
arch/arm/Kconfig
View file

@ -1317,8 +1317,16 @@ config ARCH_CHIP
default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X
default "sam34" if ARCH_CHIP_SAM34
default "samv7" if ARCH_CHIP_SAMV7
default "stm32" if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1
default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0
default "stm32f1" if ARCH_CHIP_STM32F1
default "stm32f2" if ARCH_CHIP_STM32F2
default "stm32f3" if ARCH_CHIP_STM32F3
default "stm32f4" if ARCH_CHIP_STM32F4
default "stm32g4" if ARCH_CHIP_STM32G4
default "stm32l1" if ARCH_CHIP_STM32L1
default "stm32f0" if ARCH_CHIP_STM32F0
default "stm32l0" if ARCH_CHIP_STM32L0
default "stm32g0" if ARCH_CHIP_STM32G0
default "stm32c0" if ARCH_CHIP_STM32C0
default "stm32f7" if ARCH_CHIP_STM32F7
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
@ -1819,11 +1827,35 @@ endif
if ARCH_CHIP_SAMV7
source "arch/arm/src/samv7/Kconfig"
endif
if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1
source "arch/arm/src/stm32/Kconfig"
if ARCH_CHIP_STM32F1
source "arch/arm/src/stm32f1/Kconfig"
endif
if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0
source "arch/arm/src/stm32f0l0g0/Kconfig"
if ARCH_CHIP_STM32F2
source "arch/arm/src/stm32f2/Kconfig"
endif
if ARCH_CHIP_STM32F3
source "arch/arm/src/stm32f3/Kconfig"
endif
if ARCH_CHIP_STM32F4
source "arch/arm/src/stm32f4/Kconfig"
endif
if ARCH_CHIP_STM32G4
source "arch/arm/src/stm32g4/Kconfig"
endif
if ARCH_CHIP_STM32L1
source "arch/arm/src/stm32l1/Kconfig"
endif
if ARCH_CHIP_STM32F0
source "arch/arm/src/stm32f0/Kconfig"
endif
if ARCH_CHIP_STM32L0
source "arch/arm/src/stm32l0/Kconfig"
endif
if ARCH_CHIP_STM32G0
source "arch/arm/src/stm32g0/Kconfig"
endif
if ARCH_CHIP_STM32C0
source "arch/arm/src/stm32c0/Kconfig"
endif
if ARCH_CHIP_STM32F7
source "arch/arm/src/stm32f7/Kconfig"

2756
arch/arm/include/stm32/chip.h
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/****************************************************************************
* arch/arm/include/stm32l1/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32L1_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32L1_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* Get customizations for each supported chip and provide alternate function
* pin-mapping
*
* NOTE: Each GPIO pin may serve either for general purpose I/O or for a
* special alternate function (such as USART, CAN, USB, SDIO, etc.). That
* particular pin-mapping will depend on the package and STM32 family. If
* you are incorporating a new STM32 chip into NuttX, you will need to add
* the pin-mapping to a header file and to include that header file below.
* The chip-specific pin-mapping is defined in the chip datasheet.
*/
/* STM32L EnergyLite Line ***************************************************/
/* STM32L151XX -- No LCD
* STM32L152XX -- With LCD
*
* STM32L15XCX -- 48-pins
* STM32L15XRX -- 64-pins
* STM32L15XVX -- 100-pins
* STM32L15XZX -- 144-pins
*
* STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM
* STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM
* STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM
*
* STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density)
*
* STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density)
* STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density)
*/
#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \
defined(CONFIG_ARCH_CHIP_STM32L151CB)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 37 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 14-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \
defined(CONFIG_ARCH_CHIP_STM32L151RB)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 51 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 20-channels */
# define STM32_NDAC 2 /* DAC , 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \
defined(CONFIG_ARCH_CHIP_STM32L151VB)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 24-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \
defined(CONFIG_ARCH_CHIP_STM32L152CB)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x18 */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 37 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 14-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \
defined(CONFIG_ARCH_CHIP_STM32L152RB)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x32, 8x28 */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 51 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 20-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \
defined(CONFIG_ARCH_CHIP_STM32L152VB)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 24-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152CC)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x18 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 37 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 14-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152RC)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x32, 8x28 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 51 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 21-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152VC)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 25-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 51 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 25-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 25-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 109 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 25-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 115 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 25-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD)
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA
* 32-bit general timer TIM5 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 5 /* USART1-3, UART4-5 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 115 /* GPIOA-G,H */
# define STM32_NADC 1 /* ADC1, 40-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L162VE)
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA
* 32-bit general timer TIM5 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 12-channels */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 5 /* USART1-3, UART4-5 */
# define STM32_NLPUART 0 /* No LPUART */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-G,H */
# define STM32_NADC 1 /* ADC1, 25-channels */
# define STM32_NDAC 2 /* DAC 1, 2 channels */
# define STM32_NCMP 2 /* (2) Comparators */
# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
/* STM32 F100 Value Line ****************************************************/
#else
# error "Unsupported STM32 chip"
#endif
/* Peripheral IP versions ***************************************************/
/* Peripheral IP versions are invariant and should be decided here, not in
* Kconfig.
*
* REVISIT: Currently only SPI IP version is handled here, with others being
* handled in Kconfig. Those others need to be gradually refactored
* and resolved here.
*/
#define STM32_HAVE_IP_SPI_V1
/* NVIC priority levels *****************************************************/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_STM32L1_CHIP_H */

86
arch/arm/include/stm32/stm32l15xxx_irq.h → arch/arm/include/stm32l1/irq.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/stm32/stm32l15xxx_irq.h
* arch/arm/include/stm32l1/irq.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,12 +20,12 @@
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32L1_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32L1_IRQ_H
/****************************************************************************
* Included Files
@ -33,22 +33,45 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32l1/chip.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be
* found in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16) for low and medium density devices
/* IRQ numbers.
* The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*/
#if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY)
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16).
* These definitions are chip-specific
*/
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
/****************************************************************************
* Included Files
****************************************************************************/
#if defined(CONFIG_STM32L1_LOWDENSITY) || defined(CONFIG_STM32L1_MEDIUMDENSITY)
# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */
@ -98,8 +121,6 @@
# define STM32_IRQ_NEXTINTS (45)
/* External interrupts (vectors >= 16) medium+ density devices */
#elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY)
# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
@ -160,9 +181,7 @@
# define STM32_IRQ_NEXTINTS (54)
/* External interrupts (vectors >= 16) high density devices */
#elif defined(CONFIG_STM32_HIGHDENSITY)
#elif defined(CONFIG_STM32L1_HIGHDENSITY)
# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */
@ -230,31 +249,4 @@
# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32L1_IRQ_H */

17
arch/arm/src/common/stm32/CMakeLists.txt
View file

@ -227,9 +227,8 @@ if(CONFIG_STM32_COMMON_LEGACY)
endif()
endif()
if(CONFIG_STM32_ADC
AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1
OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2))
if(CONFIG_STM32_ADC AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1
OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2))
list(APPEND SRCS stm32_adc_m3m4_v1v2.c)
endif()
@ -237,9 +236,8 @@ if(CONFIG_STM32_COMMON_LEGACY)
list(APPEND SRCS stm32_sdadc_m3m4_v1.c)
endif()
if(CONFIG_STM32_DAC
AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1
OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2))
if(CONFIG_STM32_DAC AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1
OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2))
list(APPEND SRCS stm32_dac_m3m4_v1.c)
endif()
@ -358,12 +356,7 @@ if(CONFIG_STM32_COMMON_LEGACY)
endif()
if(CONFIG_ARCH_CORTEXM0)
list(
APPEND
SRCS
stm32_irq_m0_v1.c
stm32_start_m0_v1.c
stm32_lsi_m0_v1.c)
list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c)
if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1)
list(APPEND SRCS stm32_gpio_m0_v1.c)

2
arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c
View file

@ -1093,7 +1093,7 @@ int stm32_dma2dinitialize(void)
stm32_dma2duninitialize();
/* Enable dma2d is done in rcc_enableahb1, see
* arch/arm/src/stm32/stm32f40xxx_rcc.c
* arch/arm/src/stm32f4/stm32_rcc.c
*/
#ifdef CONFIG_STM32_FB_CMAP

2
arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c
View file

@ -20,7 +20,7 @@
*
****************************************************************************/
/* Ported from arch/arm/src/stm32/stm32_dma_v1mux.c */
/* Ported from arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c */
/****************************************************************************
* Included Files

2
arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c
View file

@ -47,7 +47,7 @@
#include "stm32_gpio.h"
#include "stm32_rcc.h"
/* Ported from arch/arm/src/stm32/stm32_fdcan.c */
/* Ported from arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c */
/****************************************************************************
* Pre-processor Definitions

57
arch/arm/src/stm32/CMakeLists.txt
View file

@ -1,57 +0,0 @@
# ##############################################################################
# arch/arm/src/stm32/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
set(SRCS)
list(
APPEND
SRCS
stm32_allocateheap.c
stm32_start.c
stm32_rcc.c
stm32_lse.c
stm32_lsi.c
stm32_irq.c
stm32_lowputc.c)
if(CONFIG_STM32_TICKLESS_TIMER)
list(APPEND SRCS stm32_tickless.c)
else()
list(APPEND SRCS stm32_timerisr.c)
endif()
if(CONFIG_BUILD_PROTECTED)
list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c)
endif()
if(NOT CONFIG_ARCH_IDLE_CUSTOM)
list(APPEND SRCS stm32_idle.c)
endif()
list(APPEND SRCS stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c)
if(NOT CONFIG_ARCH_CUSTOM_PMINIT)
list(APPEND SRCS stm32_pminitialize.c)
endif()
target_sources(arch PRIVATE ${SRCS})
add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common)

2675
arch/arm/src/stm32/Kconfig
View file

File diff suppressed because it is too large Load diff

206
arch/arm/src/stm32/hardware/stm32f10xxx_uart.h
View file

@ -1,206 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32f10xxx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Status register */
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
#define USART_SR_ALLBITS (0x03ff)
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
/* Data register */
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Control register 1 */
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
/* Control register 2 */
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Compatibility definitions ************************************************/
/* F3 Transmit/Read registers */
#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H */

218
arch/arm/src/stm32/hardware/stm32f20xxx_uart.h
View file

@ -1,218 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32f20xxx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 5
# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Status register */
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
#define USART_SR_ALLBITS (0x03ff)
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
/* Data register */
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Control register 1 */
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
/* Control register 2 */
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Compatibility definitions ************************************************/
/* F3 Transmit/Read registers */
#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H */

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arch/arm/src/stm32/hardware/stm32f30xxx_uart.h
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@ -1,341 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32f30xxx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET)
# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET)
# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET)
# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET)
# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET)
# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET)
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET)
# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET)
# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET)
# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET)
# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET)
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET)
# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET)
# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET)
# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */
#define USART_CR1_M (1 << 12) /* Bit 12: Word length */
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */
#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT)
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */
#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT)
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */
#define USART_CR1_ALLINTS \
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\
USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE)
/* Control register 2 */
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */
# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */
# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */
# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */
#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT)
#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */
#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT)
#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */
#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT)
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */
#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */
#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT)
#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
# define USART_CR3_WUS_ADDRMAT (0 << USART_CR3_WUS_SHIFT) /* Active on address match */
# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */
# define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
/* Baud Rate Register */
#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/
#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT)
#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */
#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT)
#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/
#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT)
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Receiver timeout register */
#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
/* Request register */
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */
#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */
/* Interrupt & status register */
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */
#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */
#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */
#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */
#define USART_ISR_ALLBITS (0x007fdfff)
/* Interrupt flag clear register */
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
#define USART_ICR_ALLBITS (0x00121b5f)
/* Receive data register */
#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */
#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
/* Transmit data register */
#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
/* Compatibility definitions ************************************************/
/* F1/F2/F4 Status register */
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
#define USART_SR_PE USART_ISR_PE /* Parity Error */
#define USART_SR_FE USART_ISR_FE /* Framing error */
#define USART_SR_NE USART_ISR_NF /* Noise detected flag */
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */
#define USART_SR_ALLBITS USART_ISR_ALLBITS
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H */

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arch/arm/src/stm32/hardware/stm32f40xxx_uart.h
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@ -1,236 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32f40xxx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 5
# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 6
# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 7
# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Status register */
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
#define USART_SR_ALLBITS (0x03ff)
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
/* Data register */
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Control register 1 */
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
/* Control register 2 */
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Compatibility definitions ************************************************/
/* F3 Transmit/Read registers */
#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H */

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arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h
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@ -1,439 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */
#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */
#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */
#define STM32_USART_BRR_OFFSET 0x000c /* BAUD Rate Register */
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */
#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt Flag Clear Register */
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */
/* Register Addresses *******************************************************/
#if (STM32_NLPUART > 0)
# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_LPUART1_BRR (STM32_LPUART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_LPUART1_RQR (STM32_LPUART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_LPUART1_ISR (STM32_LPUART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_LPUART1_ICR (STM32_LPUART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_LPUART1_RDR (STM32_LPUART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_LPUART1_TDR (STM32_LPUART1_BASE + STM32_USART_TDR_OFFSET)
# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if (STM32_NUSART > 0)
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if (STM32_NUSART > 1)
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if (STM32_NUSART > 2)
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if (STM32_NUSART > 3)
# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if (STM32_NUSART > 4)
# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control Register 1 */
#define USART_CR1_UE (1 << 0) /* Bit 0 - USART Enable */
#define USART_CR1_UESM (1 << 1) /* Bit 1 - USART Enable in low power Mode */
#define USART_CR1_RE (1 << 2) /* Bit 2 - Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3 - Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4 - IDLE Interrupt Enable */
#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5 in FIFO mode - Rx FIFO Not Empty Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5 in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6 - Transmission Complete Interrupt Enable */
#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7 in FIFO mode - Tx FIFO Not Full Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7 in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8 - PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9 - Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10 - Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11 - Receiver Wakeup method */
#define USART_CR1_M0 (1 << 12) /* Bit 12 - Word length - Bit 0 */
#define USART_CR1_MME (1 << 13) /* Bit 13 - Mute Mode Enable */
#define USART_CR1_CMIE (1 << 14) /* Bit 14 - Character match interrupt enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15 - Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK)
#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK)
#define USART_CR1_RTOIE (1 << 26) /* Bit 26 - Receive Time Out interrupt enable */
#define USART_CR1_EOBIE (1 << 27) /* Bit 27 - End of Block interrupt enable */
#define USART_CR1_M1 (1 << 28) /* Bit 28 - Word length - Bit 1 */
#define USART_CR1_FIFOEN (1 << 29) /* Bit 29 - FIFO mode enable */
#define USART_CR1_TXFEIE (1 << 30) /* Bit 30 - TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE (1 << 31) /* Bit 31 - RXFIFO Full interrupt enable */
#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1)
#define USART_CR1_ALLINTS \
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \
USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | \
USART_CR1_EOBIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE)
#define LPUART_CR1_ALLINTS \
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \
USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \
USART_CR1_TXFEIE | USART_CR1_RXFFIE)
/* Control Register 2 */
#define USART_CR2_SLVEN (1 << 0) /* Synchronous Slave Mode Enable */
#define USART_CR2_DIS_NSS (1 << 3) /* Slave Select (NSS) Pin Ignore For SPI */
#define USART_CR2_ADDM7 (1 << 4) /* 7-Bit / 4-Bit Address Detection */
#define USART_CR2_LBDL (1 << 5) /* LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Stop Bit Mode */
#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 1 Stop Bit */
# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 0.5 Stop Bit */
# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 2 Stop Bits */
# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 1.5 Stop Bits */
#define USART_CR2_LINEN (1 << 14) /* LIN Mode Enable */
#define USART_CR2_SWAP (1 << 15) /* Swap TX/RX Pins */
#define USART_CR2_RXINV (1 << 16) /* RX Pin Active Level Inversion */
#define USART_CR2_TXINV (1 << 17) /* TX Pin Active Level Inversion */
#define USART_CR2_DATAINV (1 << 18) /* Binary Data Inversion */
#define USART_CR2_MSBFIRST (1 << 19) /* MSB First */
#define USART_CR2_ABREN (1 << 20) /* Auto BAUD-Rate Enable */
#define USART_CR2_ABRMOD_SHIFT (21) /* Auto BAUD-Rate Detection Mode */
#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT)
# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* Measurement of Start Bit */
# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* Falling Edge To Falling Edge */
# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 0X7F Frame Detection */
# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 0X55 Frame Detection */
#define USART_CR2_RTOEN (1 << 23) /* Receiver Time-Out Enable */
#define USART_CR2_ADD8_SHIFT (24) /* Address of the USART Node */
#define USART_CR2_ADD8_MASK (0xff << USART_CR2_ADD8_SHIFT)
/* Control Register 3 */
#define USART_CR3_EIE (1 << 0) /* Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* IrDA Mode Enable */
#define USART_CR3_IRLP (1 << 2) /* IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* SmartCard NACK Enable */
#define USART_CR3_SCEN (1 << 5) /* SmartCard Mode Enable */
#define USART_CR3_DMAR (1 << 6) /* DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* One Sample Bit Method Enable */
#define USART_CR3_OVRDIS (1 << 12) /* Overrun Disable */
#define USART_CR3_DDRE (1 << 13) /* DMA Disable on Reception Error */
#define USART_CR3_DEM (1 << 14) /* Driver Enable Mode */
#define USART_CR3_DEP (1 << 15)
#define USART_CR3_SCARCNT_SHIFT (17) /* SmartCard Auto-Retry Count */
#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT)
# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK)
#define USART_CR3_WUS_SHIFT (20) /* Wake Up From Low Power Mode Interrupt Flag Selection) */
#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT)
# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* On Address Match */
# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* On Start Bit Detection */
# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* On RXNE/RXFNE */
#define USART_CR3_WUFIE (1 << 22) /* Wake Up From Low Power Mode Interrupt Enable */
#define USART_CR3_TXFTIE (1 << 23) /* Transmit FIFO Threshold Interrupt Enable */
#define USART_CR3_TCBGTIE (1 << 24) /* Transmit Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_SHIFT (25) /* Receive FIFO Threshold Configuration */
#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT)
# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/8Th Depth */
# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/4Th Depth */
# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/2 Depth */
# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 3/4Ths Depth */
# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 7/8Ths Depth */
# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Is Full */
#define USART_CR3_RXFTIE (1 << 28) /* Receive FIFO Threshold Interrupt Enable */
#define USART_CR3_TXFTCFG_SHIFT (29) /* Transmit FIFO Threshold Configuration */
#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT)
# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/8Th Depth */
# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/4Th Depth */
# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/2 Depth */
# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 3/4Ths Depth */
# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 7/8Ths Depth */
# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Is Full */
/* BAUD Rate Register */
/* Full BRR field */
#define USART_BRR_SHIFT (0)
#define USART_BRR_MASK (0xffff << USART_BRR_BRR_SHIFT)
# define USART_BRR(n) (((n) << USART_BRR_BRR_SHIFT) & USART_BRR_BRR_MASK)
/* Partial BRR field BRR[3:0]:
*
* When OVER8 = 0: BRR[3:0] = USARTDIV[3:0]
*
* When OVER8 = 1: BRR[2:0] = (USARTDIV[3:0] >> 1) and
* BRR[3] must be kept cleared.
*/
#define USART_BRR_0_3_SHIFT (0)
#define USART_BRR_0_3_MASK (0xf << USART_BRR_0_3_SHIFT)
# define USART_BRR_0_3(n) (((n) << USART_BRR_0_3_SHIFT) & USART_BRR_0_3_MASK)
/* Partial BRR field BRR[15:4]:
* BRR[15:4] = USARTDIV[15:4]
*/
#define USART_BRR_4_15_SHIFT (4)
#define USART_BRR_4_15_MASK (0xfff << USART_BRR_4_15_SHIFT)
# define USART_BRR_4_15(n) (((n) << USART_BRR_4_15_SHIFT) & USART_BRR_4_15_MASK)
/* Guard Time and Prescaler Register */
#define USART_GTPR_PSC_SHIFT (0) /* Prescaler Value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK)
#define USART_GTPR_GT_SHIFT (8) /* Guard Time Value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK)
/* Receiver Timeout Register */
#define USART_RTOR_RTO_SHIFT (0) /* Receiver Time Out Value */
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK)
#define USART_RTOR_BLEN_SHIFT (24) /* Block Length */
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK)
/* Request Register */
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */
#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */
/* Interrupt and Status Register */
#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */
#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */
#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */
#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */
#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */
#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */
#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */
#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */
#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */
#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */
#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */
#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */
#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */
#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */
#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */
#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */
#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto BAUD Rate Error */
#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto BAUD Rate Flag */
#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */
#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */
#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */
#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */
#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */
#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */
#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */
#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */
#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */
#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Flag */
#define USART_ISR_ALLBITS (0x0fffffff)
/* Interrupt Flag Clear Register */
#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */
#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */
#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */
#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */
#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */
#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */
#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */
#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */
#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */
#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */
/* Receive Data Register */
#define USART_RDR_SHIFT (0)
#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK)
/* Transmit Data Register */
#define USART_TDR_SHIFT (0)
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK)
/* Prescaler Register */
#define USART_PRESC_PRESCALER_SHIFT (0)
#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT)
#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT)
/* Compatibility definitions ************************************************/
/* Compatibility with F1/F2/F4 Status Register names */
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
#define USART_SR_PE USART_ISR_PE /* Parity Error */
#define USART_SR_FE USART_ISR_FE /* Framing error */
#define USART_SR_NE USART_ISR_NE /* Noise detected flag */
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */
#define USART_SR_ALLBITS USART_ISR_ALLBITS
#define USART_CR1_M USART_CR1_M0
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H */

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arch/arm/src/stm32/hardware/stm32l15xxx_uart.h
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/****************************************************************************
* arch/arm/src/stm32/hardware/stm32l15xxx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Status register */
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
#define USART_SR_ALLBITS (0x03ff)
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
/* Data register */
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_DR_MASK (0x1ff << USART_DR_SHIFT)
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Control register 1 */
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
/* Control register 2 */
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Compatibility definitions ************************************************/
/* L15 Transmit/Read registers */
#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H */

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arch/arm/src/stm32/stm32_pm.h
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/****************************************************************************
* arch/arm/src/stm32/stm32_pm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_PM_H
#define __ARCH_ARM_SRC_STM32_STM32_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_pmstop
*
* Description:
* Enter STOP mode.
*
* Input Parameters:
* lpds - true: To further reduce power consumption in Stop mode, put the
* internal voltage regulator in low-power mode using the LPDS bit
* of the Power control register (PWR_CR).
*
* Returned Value:
* Zero means that the STOP was successfully entered and the system has
* been re-awakened. The internal voltage regulator is back to its
* original state. Otherwise, STOP mode did not occur and a negated
* errno value is returned to indicate the cause of the failure.
*
****************************************************************************/
int stm32_pmstop(bool lpds);
/****************************************************************************
* Name: stm32_pmstandby
*
* Description:
* Enter STANDBY mode.
*
* Input Parameters:
* None
*
* Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
* failure.
*
****************************************************************************/
int stm32_pmstandby(void);
/****************************************************************************
* Name: stm32_pmsleep
*
* Description:
* Enter SLEEP mode.
*
* Input Parameters:
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
* mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* None
*
****************************************************************************/
void stm32_pmsleep(bool sleeponexit);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_PM_H */

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arch/arm/src/stm32/stm32_rcc.h
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/****************************************************************************
* arch/arm/src/stm32/stm32_rcc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32_STM32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "chip.h"
#if defined(CONFIG_STM32_STM32L15XX)
# include "hardware/stm32l15xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F10XX)
# include "hardware/stm32f10xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "hardware/stm32f20xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F30XX)
# include "hardware/stm32f30xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F33XX)
# include "hardware/stm32f33xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "hardware/stm32f37xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "hardware/stm32f40xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32G4XXX)
# include "hardware/stm32g4xxxx_rcc.h"
#else
# error "Unsupported STM32 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_mco1config
*
* Description:
* Selects the clock source to output on MCO1 pin (PA8). PA8 should be
* configured in alternate function mode.
*
* Input Parameters:
* source - One of the definitions for the RCC_CFGR_MCO1 definitions from
* chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1_HSI, RCC_CFGR_MCO1_LSE,
* RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1_PLL}
* div - One of the definitions for the RCC_CFGR_MCO1PRE definitions from
* chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1PRE_NONE, RCC_CFGR_MCO1PRE_DIV2,
* RCC_CFGR_MCO1PRE_DIV3, RCC_CFGR_MCO1PRE_DIV4, RCC_CFGR_MCO1PRE_DIV5}
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
static inline void stm32_mco1config(uint32_t source, uint32_t div)
{
uint32_t regval;
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK);
regval |= (source | div);
putreg32(regval, STM32_RCC_CFGR);
}
#endif
/****************************************************************************
* Name: stm32_mcoconfig
*
* Description:
* Selects the clock source to output on MC pin (PA8) for stm32f10xxx.
* PA8 should be configured in alternate function mode.
*
* Input Parameters:
* source - One of the definitions for the RCC_CFGR_MCO definitions from
* chip/stm32f10xxx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK,
* RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK,
* RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK}
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_STM32_CONNECTIVITYLINE)
static inline void stm32_mcoconfig(uint32_t source)
{
uint32_t regval;
/* Set MCO source */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_MCO_MASK);
regval |= (source & RCC_CFGR_MCO_MASK);
putreg32(regval, STM32_RCC_CFGR);
}
#endif
/****************************************************************************
* Name: stm32_mcodivconfig
*
* Description:
* Selects the clock source to output and clock divider on MC pin (PA4) for
* stm32l1xxx. PA4 should be configured in alternate function mode.
*
* Input Parameters:
* source - One of the definitions for the RCC_CFGR_MCOSEL definitions
* from chip/stm32l15xxx_rcc.h
* {RCC_CFGR_MCOSEL_DISABLED, RCC_CFGR_MCOSEL_SYSCLK,
* RCC_CFGR_MCOSEL_HSICLK, RCC_CFGR_MCOSEL_MSICLK,
* RCC_CFGR_MCOSEL_HSECLK, RCC_CFGR_MCOSEL_PLLCLK,
* RCC_CFGR_MCOSEL_LSICLK, RCC_CFGR_MCOSEL_LSECLK}
* divider - One of the definitions for the RCC_CFGR_MCOPRE definitions
* from chip/stm32l15xxx_rcc.h
* {RCC_CFGR_MCOPRE_DIV1, RCC_CFGR_MCOPRE_DIV2,
* RCC_CFGR_MCOPRE_DIV4, RCC_CFGR_MCOPRE_DIV8, RCC_CFGR_MCOPRE_DIV16}
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32L15XX)
static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider)
{
uint32_t regval;
/* Set MCO source */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_MCOSEL_MASK);
regval |= (source & RCC_CFGR_MCOSEL_MASK);
regval &= ~(RCC_CFGR_MCOPRE_MASK);
regval |= (divider & RCC_CFGR_MCOPRE_MASK);
putreg32(regval, STM32_RCC_CFGR);
}
#endif
/****************************************************************************
* Name: stm32_mco2config
*
* Description:
* Selects the clock source to output on MCO2 pin (PC9). PC9 should be
* configured in alternate function mode.
*
* Input Parameters:
* source - One of the definitions for the RCC_CFGR_MCO2 definitions from
* chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2_SYSCLK, RCC_CFGR_MCO2_PLLI2S,
* RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2_PLL}
* div - One of the definitions for the RCC_CFGR_MCO2PRE definitions from
* chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2PRE_NONE, RCC_CFGR_MCO2PRE_DIV2,
* RCC_CFGR_MCO2PRE_DIV3, RCC_CFGR_MCO2PRE_DIV4, RCC_CFGR_MCO2PRE_DIV5}
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
static inline void stm32_mco2config(uint32_t source, uint32_t div)
{
uint32_t regval;
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK);
regval |= (source | div);
putreg32(regval, STM32_RCC_CFGR);
}
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32_clockconfig(void);
/****************************************************************************
* Name: stm32_board_clockconfig
*
* Description:
* Any STM32 board may replace the "standard" board clock configuration
* logic with its own, custom clock configuration logic.
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_board_clockconfig(void);
#endif
/****************************************************************************
* Name: stm32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h.
* This function is only available to support low-power modes of operation:
* When re-awakening from deep-sleep modes, it is necessary to re-enable/
* re-start the PLL
*
* This functional performs a subset of the operations performed by
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32_clockenable(void);
#endif
/****************************************************************************
* Name: stm32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32_rcc_enablelse(void);
/****************************************************************************
* Name: stm32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_enablelsi(void);
/****************************************************************************
* Name: stm32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_disablelsi(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_RCC_H */

63
arch/arm/src/stm32/stm32_userspace.h
View file

@ -1,63 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_userspace.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H
#define __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32_userspace(void);
#endif
#endif /* __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H */

2
arch/arm/src/stm32f7/stm32_can_sock.c
View file

@ -49,7 +49,7 @@
#include "stm32_rcc.h"
#include "stm32_can.h"
/* Ported form arch/arm/src/stm32/stm32_can_sock.c */
/* Ported form arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c */
/****************************************************************************
* Pre-processor Definitions

3
arch/arm/src/stm32f7/stm32_foc.c
View file

@ -78,7 +78,8 @@
*
* Currently, up to two FOC instances are supported.
*
* This implementation is based on arch/arm/src/stm32/stm32_foc.c
* This implementation is based on
* arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c
*/
/* Verify system configuration **********************************************/

9
boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt → arch/arm/src/stm32l1/CMakeLists.txt
View file

@ -1,5 +1,5 @@
# ##############################################################################
# boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt
# arch/arm/src/stm32l1/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
@ -20,4 +20,9 @@
#
# ##############################################################################
add_subdirectory(src)
set(SRCS)
list(APPEND SRCS stm32_rcc.c)
target_sources(arch PRIVATE ${SRCS})
add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common)

356
arch/arm/src/stm32l1/Kconfig Normal file
View file

@ -0,0 +1,356 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "STM32 L1 configuration"
if ARCH_CHIP_STM32L1
choice
prompt "STM32L1 Chip Selection"
depends on ARCH_CHIP_STM32L1
config ARCH_CHIP_STM32L151C6
bool "STM32L151C6"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151C8
bool "STM32L151C8"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151CB
bool "STM32L151CB"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151R6
bool "STM32L151R6"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151R8
bool "STM32L151R8"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151RB
bool "STM32L151RB"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151V6
bool "STM32L151V6"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151V8
bool "STM32L151V8"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L151VB
bool "STM32L151VB"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM
config ARCH_CHIP_STM32L152C6
bool "STM32L152C6"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with
4x18 LCD interface
config ARCH_CHIP_STM32L152C8
bool "STM32L152C8"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with
4x18 LCD interface
config ARCH_CHIP_STM32L152CB
bool "STM32L152CB"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with
4x18 LCD interface
config ARCH_CHIP_STM32L152R6
bool "STM32L152R6"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152R8
bool "STM32L152R8"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152RB
bool "STM32L152RB"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152V6
bool "STM32L152V6"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L152V8
bool "STM32L152V8"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L152VB
bool "STM32L152VB"
select STM32_STM32L15XX
select STM32L1_LOWDENSITY
---help---
STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L152CC
bool "STM32L152CC"
select STM32_STM32L15XX
select STM32L1_MEDIUMPLUSDENSITY
---help---
STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with
4x18 LCD interface
config ARCH_CHIP_STM32L152RC
bool "STM32L152RC"
select STM32_STM32L15XX
select STM32L1_MEDIUMPLUSDENSITY
---help---
STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152VC
bool "STM32L152VC"
select STM32_STM32L15XX
select STM32L1_MEDIUMPLUSDENSITY
---help---
STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L151RE
bool "STM32L151RE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L152RE
bool "STM32L152RE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L151VE
bool "STM32L151VE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L152VE
bool "STM32L152VE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L151QE
bool "STM32L151QE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L152QE
bool "STM32L152QE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L151ZE
bool "STM32L151ZE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L152ZE
bool "STM32L152ZE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
config ARCH_CHIP_STM32L162ZD
bool "STM32L162ZD"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
select STM32_HAVE_AES
---help---
STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L162VE
bool "STM32L162VE"
select STM32_STM32L15XX
select STM32L1_HIGHDENSITY
select STM32_HAVE_AES
---help---
STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with
4x44/8x40 LCD interface
endchoice
endif
config STM32_STM32L15XX
bool
default n
select STM32_HAVE_DMA1
select STM32_HAVE_COMP
select STM32_HAVE_DMA2
select ARCH_CORTEXM3
select STM32_ENERGYLITE
select STM32_HAVE_I2C1
select STM32_HAVE_LCD
select STM32_HAVE_SPI1
select STM32_HAVE_SYSCFG
select STM32_HAVE_USART1
select STM32_HAVE_USART2
select STM32_HAVE_USBDEV
select STM32_HAVE_DAC1
select STM32_HAVE_I2C2
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_TIM2
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_ADC2
select STM32_HAVE_USART3
select STM32_HAVE_RTC_SUBSECONDS if !STM32L1_LOWDENSITY
select STM32_HAVE_RTC_MAGIC
select STM32_HAVE_RTC
select STM32_HAVE_CRC
select STM32_HAVE_PWR
select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES
select STM32_HAVE_IP_BBSRAM_M3M4_V1
select STM32_HAVE_IP_BKP_M3M4_V1
select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1
select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM
select STM32_HAVE_IP_CRYPTO_M3M4_V1
select STM32_HAVE_IP_DBGMCU_M3M4_V2
select STM32_HAVE_IP_ADC_M3M4_V1
select STM32_HAVE_COMMON_FOC
select STM32_HAVE_IP_DCMI_V1
select STM32_HAVE_IP_DAC_M3M4_V1
select STM32_HAVE_IP_DFUMODE_M3M4_V1
select STM32_HAVE_IP_DMA_V1
select STM32_HAVE_IP_DMA_V1_8CH
select STM32_HAVE_IP_EXTI_V1
select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC
select STM32_HAVE_IP_FLASH_M3M4_V1
select STM32_HAVE_IP_FLASH_M3M4_L1
select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC
select STM32_HAVE_IP_FREERUN_M3M4_V1
select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC
select STM32_HAVE_IP_GPIO_M3M4_V1
select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1
select STM32_HAVE_IP_I2C_M3M4_V1
select STM32_HAVE_IP_I2S_M3M4_V1
select STM32_HAVE_IP_ONESHOT_M3M4_V1
select STM32_HAVE_IP_PWR_M3M4_V1
select STM32_HAVE_IP_RTC_M3M4_V1
select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER
select STM32_HAVE_IP_SDIO_M3M4_V1
select STM32_HAVE_IP_SPI_V1
select STM32_HAVE_IP_SYSCFG_M3M4_V1
select STM32_HAVE_IP_TIMERS_M3M4_V1
select STM32_HAVE_IP_UID_M3M4_V1
select STM32_HAVE_IP_USART_V2
select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV
select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS
select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS
select STM32_HAVE_IP_WDG_M3M4_V1
config STM32L1_MEDIUMPLUSDENSITY
bool
default n
config STM32L1_HIGHDENSITY
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM2
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
config STM32L1_MEDIUMDENSITY
bool
default n
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM2
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
config STM32L1_LOWDENSITY
bool
default n
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM2
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_CAN1

25
arch/arm/src/stm32/Make.defs → arch/arm/src/stm32l1/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# arch/arm/src/stm32/Make.defs
# arch/arm/src/stm32l1/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
@ -22,27 +22,6 @@
include armv7-m/Make.defs
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
CHIP_CSRCS += stm32_lsi.c stm32_irq.c stm32_lowputc.c
ifdef CONFIG_STM32_TICKLESS_TIMER
CHIP_CSRCS += stm32_tickless.c
else
CHIP_CSRCS += stm32_timerisr.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32_idle.c
endif
CHIP_CSRCS += stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += stm32_pminitialize.c
endif
CHIP_CSRCS = stm32_rcc.c
include common/stm32/Make.defs

42
arch/arm/src/stm32/stm32_start.h → arch/arm/src/stm32l1/chip.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_start.h
* arch/arm/src/stm32l1/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_START_H
#define __ARCH_ARM_SRC_STM32_STM32_START_H
#ifndef __ARCH_ARM_SRC_STM32L1_CHIP_H
#define __ARCH_ARM_SRC_STM32L1_CHIP_H
/****************************************************************************
* Included Files
@ -29,21 +29,31 @@
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Include the chip capabilities file */
#include <arch/stm32l1/chip.h>
/* Include the chip interrupt definition file */
#include <arch/stm32l1/irq.h>
/* Include the chip memory map */
#include "hardware/stm32_memorymap.h"
/* Include the chip pinmap */
#include "hardware/stm32_pinmap.h"
/****************************************************************************
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after
* clocking and memory have been configured but before caches have been
* enabled and before any devices have been initialized.
*
* Pre-processor Definitions
****************************************************************************/
void stm32_boardinitialize(void);
/* Provide the required number of peripheral interrupt vector
* definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes
* from the chip-specific * IRQ header file included by arch/stm32/irq.h.
*/
#endif /* __ARCH_ARM_SRC_STM32_STM32_START_H */
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
#endif /* __ARCH_ARM_SRC_STM32L1_CHIP_H */

17
arch/arm/src/stm32l1/hardware/stm32_memorymap.h Normal file
View file

@ -0,0 +1,17 @@
/****************************************************************************
* arch/arm/src/stm32l1/hardware/stm32_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/stm32l15xxx_memorymap.h"
#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H */

17
arch/arm/src/stm32l1/hardware/stm32_pinmap.h Normal file
View file

@ -0,0 +1,17 @@
/****************************************************************************
* arch/arm/src/stm32l1/hardware/stm32_pinmap.h
*
* SPDX-License-Identifier: Apache-2.0
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H
#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/stm32l15xxx_pinmap.h"
#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H */

2
arch/arm/src/stm32/hardware/stm32l15xxx_aes.h → arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32l15xxx_aes.h
* arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h
*
* SPDX-License-Identifier: Apache-2.0
*

2
arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h → arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h
* arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
*

2
arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h → arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h
* arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
*

2
arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h → arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h
* arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h
*
* SPDX-License-Identifier: Apache-2.0
*

2
arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h → arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h
* arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h
*
* SPDX-License-Identifier: Apache-2.0
*

2
arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h → arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h
* arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h
*
* SPDX-License-Identifier: Apache-2.0
*

73
arch/arm/src/stm32/stm32_lowputc.h → arch/arm/src/stm32l1/stm32.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_lowputc.h
* arch/arm/src/stm32l1/stm32.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,47 +20,50 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H
#ifndef __ARCH_ARM_SRC_STM32_STM32_H
#define __ARCH_ARM_SRC_STM32_STM32_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/* Peripherals **************************************************************/
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#include "stm32_adc.h"
#include "stm32_can.h"
#include "stm32_comp.h"
#include "stm32_dbgmcu.h"
#include "stm32_dma.h"
#include "stm32_dac_m3m4_v1.h"
#include "stm32_exti.h"
#include "stm32_flash.h"
#include "stm32_fmc_m3m4_v1.h"
#include "stm32_fsmc_m3m4_v1.h"
#include "stm32_gpio.h"
#include "stm32_i2c.h"
#include "stm32_ltdc_m3m4_v1.h"
#include "stm32_opamp_m3m4_v1.h"
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_rtc.h"
#include "stm32_sdio_m3m4_v1.h"
#include "stm32_spi.h"
#include "stm32_i2s.h"
#include "stm32_tim.h"
#include "stm32_uart.h"
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
# include "stm32_usbdev.h"
#endif
#include "stm32_wdg.h"
#include "stm32_lowputc.h"
#include "stm32_eth_m3m4_v1.h"
/****************************************************************************
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start.
* Performs low level initialization of serial console.
*
****************************************************************************/
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H */
#endif /* __ARCH_ARM_SRC_STM32_STM32_H */

234
arch/arm/src/stm32l1/stm32_rcc.c Normal file
View file

@ -0,0 +1,234 @@
/****************************************************************************
* arch/arm/src/stm32l1/stm32_rcc.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <nuttx/debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_rcc.h"
#include "stm32_rtc.h"
#include "stm32_flash.h"
#include "stm32.h"
#include "stm32_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
"Configure BOARD_LOOPSPERMSEC to non-default value.");
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/****************************************************************************
* Included Files
****************************************************************************/
/* Include chip-specific clocking initialization logic */
#include "stm32l15xxx_rcc.c"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_STM32_STM32L15XX)
# define STM32_RCC_XXX STM32_RCC_CSR
# define RCC_XXX_YYYRST RCC_CSR_RTCRST
#else
# define STM32_RCC_XXX STM32_RCC_BDCR
# define RCC_XXX_YYYRST RCC_BDCR_BDRST
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rcc_resetbkp
*
* Description:
* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
* the Backup Domain renders to disabling the LSE as consequence.
* In order to avoid resetting the Backup Domain when we already
* configured LSE we will reset the Backup Domain early (here).
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX)
static inline void rcc_resetbkp(void)
{
uint32_t regval;
/* Check if the RTC is already configured */
stm32_pwr_initbkp(false);
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
{
stm32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
*/
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
stm32_pwr_enablebkp(false);
}
}
#else
# define rcc_resetbkp()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32_clockconfig(void)
{
/* Make sure that we are starting in the reset state */
rcc_reset();
/* Reset backup domain if appropriate */
rcc_resetbkp();
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
stm32_stdclockconfig();
#endif
/* Enable peripheral clocking */
rcc_enableperipherals();
#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION
/* Enable I/O Compensation */
stm32_iocompensation();
#endif
}
/****************************************************************************
* Name: stm32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings
* in board.h. This function is only available to support low-power
* modes of operation: When re-awakening from deep-sleep modes, it is
* necessary to re-enable/re-start the PLL
*
* This functional performs a subset of the operations performed by
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
stm32_stdclockconfig();
#endif
}
#endif

2
arch/arm/src/stm32/stm32l15xxx_alarm.h → arch/arm/src/stm32l1/stm32l15xxx_alarm.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32l15xxx_alarm.h
* arch/arm/src/stm32l1/stm32l15xxx_alarm.h
*
* SPDX-License-Identifier: Apache-2.0
*

2
arch/arm/src/stm32/stm32l15xxx_rcc.c → arch/arm/src/stm32l1/stm32l15xxx_rcc.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32l15xxx_rcc.c
* arch/arm/src/stm32l1/stm32l15xxx_rcc.c
*
* SPDX-License-Identifier: Apache-2.0
*

130
boards/Kconfig
View file

@ -4486,52 +4486,52 @@ if ARCH_BOARD_PIC32CZCA70_CURIOSITY
source "boards/arm/samv7/pic32czca70-curiosity/Kconfig"
endif
if ARCH_BOARD_B_G474E_DPOW1
source "boards/arm/stm32/b-g474e-dpow1/Kconfig"
source "boards/arm/stm32g4/b-g474e-dpow1/Kconfig"
endif
if ARCH_BOARD_B_G431B_ESC1
source "boards/arm/stm32/b-g431b-esc1/Kconfig"
source "boards/arm/stm32g4/b-g431b-esc1/Kconfig"
endif
if ARCH_BOARD_NUCLEO_G431KB
source "boards/arm/stm32/nucleo-g431kb/Kconfig"
source "boards/arm/stm32g4/nucleo-g431kb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_G431RB
source "boards/arm/stm32/nucleo-g431rb/Kconfig"
source "boards/arm/stm32g4/nucleo-g431rb/Kconfig"
endif
if ARCH_BOARD_B_L072Z_LRWAN1
source "boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig"
source "boards/arm/stm32l0/b-l072z-lrwan1/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F072RB
source "boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig"
source "boards/arm/stm32f0/nucleo-f072rb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F091RC
source "boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig"
source "boards/arm/stm32f0/nucleo-f091rc/Kconfig"
endif
if ARCH_BOARD_NUCLEO_G070RB
source "boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig"
source "boards/arm/stm32g0/nucleo-g070rb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_G071RB
source "boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig"
source "boards/arm/stm32g0/nucleo-g071rb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_G0B1RE
source "boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig"
source "boards/arm/stm32g0/nucleo-g0b1re/Kconfig"
endif
if ARCH_BOARD_NUCLEO_L073RZ
source "boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig"
source "boards/arm/stm32l0/nucleo-l073rz/Kconfig"
endif
if ARCH_BOARD_STM32F051_DISCOVERY
source "boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig"
source "boards/arm/stm32f0/stm32f051-discovery/Kconfig"
endif
if ARCH_BOARD_STM32L0538_DISCO
source "boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig"
source "boards/arm/stm32l0/stm32l0538-disco/Kconfig"
endif
if ARCH_BOARD_STM32F072_DISCOVERY
source "boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig"
source "boards/arm/stm32f0/stm32f072-discovery/Kconfig"
endif
if ARCH_BOARD_NUCLEO_C071RB
source "boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig"
source "boards/arm/stm32c0/nucleo-c071rb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_C092RC
source "boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig"
source "boards/arm/stm32c0/nucleo-c092rc/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F722ZE
source "boards/arm/stm32f7/nucleo-f722ze/Kconfig"
@ -4651,151 +4651,151 @@ if ARCH_BOARD_NUCLEO_WB55RG
source "boards/arm/stm32wb/nucleo-wb55rg/Kconfig"
endif
if ARCH_BOARD_AXOLOTI
source "boards/arm/stm32/axoloti/Kconfig"
source "boards/arm/stm32f4/axoloti/Kconfig"
endif
if ARCH_BOARD_CLICKER2_STM32
source "boards/arm/stm32/clicker2-stm32/Kconfig"
source "boards/arm/stm32f4/clicker2-stm32/Kconfig"
endif
if ARCH_BOARD_CLOUDCTRL
source "boards/arm/stm32/cloudctrl/Kconfig"
source "boards/arm/stm32f1/cloudctrl/Kconfig"
endif
if ARCH_BOARD_EMW3162
source "boards/arm/stm32/emw3162/Kconfig"
source "boards/arm/stm32f2/emw3162/Kconfig"
endif
if ARCH_BOARD_FIRE_STM32
source "boards/arm/stm32/fire-stm32v2/Kconfig"
source "boards/arm/stm32f1/fire-stm32v2/Kconfig"
endif
if ARCH_BOARD_HYMINI_STM32V
source "boards/arm/stm32/hymini-stm32v/Kconfig"
source "boards/arm/stm32f1/hymini-stm32v/Kconfig"
endif
if ARCH_BOARD_MAPLE
source "boards/arm/stm32/maple/Kconfig"
source "boards/arm/stm32f1/maple/Kconfig"
endif
if ARCH_BOARD_ET_STM32_STAMP
source "boards/arm/stm32/et-stm32-stamp/Kconfig"
source "boards/arm/stm32f1/et-stm32-stamp/Kconfig"
endif
if ARCH_BOARD_MIKROE_STM32F4
source "boards/arm/stm32/mikroe-stm32f4/Kconfig"
source "boards/arm/stm32f4/mikroe-stm32f4/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F103RB
source "boards/arm/stm32/nucleo-f103rb/Kconfig"
source "boards/arm/stm32f1/nucleo-f103rb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F207ZG
source "boards/arm/stm32/nucleo-f207zg/Kconfig"
source "boards/arm/stm32f2/nucleo-f207zg/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F302R8
source "boards/arm/stm32/nucleo-f302r8/Kconfig"
source "boards/arm/stm32f3/nucleo-f302r8/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F303RE
source "boards/arm/stm32/nucleo-f303re/Kconfig"
source "boards/arm/stm32f3/nucleo-f303re/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F303ZE
source "boards/arm/stm32/nucleo-f303ze/Kconfig"
source "boards/arm/stm32f3/nucleo-f303ze/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F334R8
source "boards/arm/stm32/nucleo-f334r8/Kconfig"
source "boards/arm/stm32f3/nucleo-f334r8/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F410RB
source "boards/arm/stm32/nucleo-f410rb/Kconfig"
source "boards/arm/stm32f4/nucleo-f410rb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F412ZG
source "boards/arm/stm32/nucleo-f412zg/Kconfig"
source "boards/arm/stm32f4/nucleo-f412zg/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F446RE
source "boards/arm/stm32/nucleo-f446re/Kconfig"
source "boards/arm/stm32f4/nucleo-f446re/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F401RE
source "boards/arm/stm32/nucleo-f401re/Kconfig"
source "boards/arm/stm32f4/nucleo-f401re/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F411RE
source "boards/arm/stm32/nucleo-f411re/Kconfig"
source "boards/arm/stm32f4/nucleo-f411re/Kconfig"
endif
if ARCH_BOARD_STM32F401RC_RS485
source "boards/arm/stm32/stm32f401rc-rs485/Kconfig"
source "boards/arm/stm32f4/stm32f401rc-rs485/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F429ZI
source "boards/arm/stm32/nucleo-f429zi/Kconfig"
source "boards/arm/stm32f4/nucleo-f429zi/Kconfig"
endif
if ARCH_BOARD_NUCLEO_L152RE
source "boards/arm/stm32/nucleo-l152re/Kconfig"
source "boards/arm/stm32l1/nucleo-l152re/Kconfig"
endif
if ARCH_BOARD_ODRIVE36
source "boards/arm/stm32/odrive36/Kconfig"
source "boards/arm/stm32f4/odrive36/Kconfig"
endif
if ARCH_BOARD_OLIMEX_STM32E407
source "boards/arm/stm32/olimex-stm32-e407/Kconfig"
source "boards/arm/stm32f4/olimex-stm32-e407/Kconfig"
endif
if ARCH_BOARD_OLIMEX_STM32H405
source "boards/arm/stm32/olimex-stm32-h405/Kconfig"
source "boards/arm/stm32f4/olimex-stm32-h405/Kconfig"
endif
if ARCH_BOARD_OLIMEX_STM32H407
source "boards/arm/stm32/olimex-stm32-h407/Kconfig"
source "boards/arm/stm32f4/olimex-stm32-h407/Kconfig"
endif
if ARCH_BOARD_OLIMEX_STM32P107
source "boards/arm/stm32/olimex-stm32-p107/Kconfig"
source "boards/arm/stm32f1/olimex-stm32-p107/Kconfig"
endif
if ARCH_BOARD_OLIMEX_STM32P207
source "boards/arm/stm32/olimex-stm32-p207/Kconfig"
source "boards/arm/stm32f2/olimex-stm32-p207/Kconfig"
endif
if ARCH_BOARD_OLIMEX_STM32P407
source "boards/arm/stm32/olimex-stm32-p407/Kconfig"
source "boards/arm/stm32f4/olimex-stm32-p407/Kconfig"
endif
if ARCH_BOARD_OLIMEXINO_STM32
source "boards/arm/stm32/olimexino-stm32/Kconfig"
source "boards/arm/stm32f1/olimexino-stm32/Kconfig"
endif
if ARCH_BOARD_OMNIBUSF4
source "boards/arm/stm32/omnibusf4/Kconfig"
source "boards/arm/stm32f4/omnibusf4/Kconfig"
endif
if ARCH_BOARD_PHOTON
source "boards/arm/stm32/photon/Kconfig"
source "boards/arm/stm32f2/photon/Kconfig"
endif
if ARCH_BOARD_SHENZHOU
source "boards/arm/stm32/shenzhou/Kconfig"
source "boards/arm/stm32f1/shenzhou/Kconfig"
endif
if ARCH_BOARD_STM3210E_EVAL
source "boards/arm/stm32/stm3210e-eval/Kconfig"
source "boards/arm/stm32f1/stm3210e-eval/Kconfig"
endif
if ARCH_BOARD_STM3220G_EVAL
source "boards/arm/stm32/stm3220g-eval/Kconfig"
source "boards/arm/stm32f2/stm3220g-eval/Kconfig"
endif
if ARCH_BOARD_STM3240G_EVAL
source "boards/arm/stm32/stm3240g-eval/Kconfig"
source "boards/arm/stm32f4/stm3240g-eval/Kconfig"
endif
if ARCH_BOARD_STM32_TINY
source "boards/arm/stm32/stm32_tiny/Kconfig"
source "boards/arm/stm32f1/stm32_tiny/Kconfig"
endif
if ARCH_BOARD_STM32_BUTTERFLY2
source "boards/arm/stm32/stm32butterfly2/Kconfig"
source "boards/arm/stm32f1/stm32butterfly2/Kconfig"
endif
if ARCH_BOARD_STM32F103_MINIMUM
source "boards/arm/stm32/stm32f103-minimum/Kconfig"
source "boards/arm/stm32f1/stm32f103-minimum/Kconfig"
endif
if ARCH_BOARD_STM32F411_MINIMUM
source "boards/arm/stm32/stm32f411-minimum/Kconfig"
source "boards/arm/stm32f4/stm32f411-minimum/Kconfig"
endif
if ARCH_BOARD_STM32F334_DISCO
source "boards/arm/stm32/stm32f334-disco/Kconfig"
source "boards/arm/stm32f3/stm32f334-disco/Kconfig"
endif
if ARCH_BOARD_STM32F3_DISCOVERY
source "boards/arm/stm32/stm32f3discovery/Kconfig"
source "boards/arm/stm32f3/stm32f3discovery/Kconfig"
endif
if ARCH_BOARD_STM32F411E_DISCO
source "boards/arm/stm32/stm32f411e-disco/Kconfig"
source "boards/arm/stm32f4/stm32f411e-disco/Kconfig"
endif
if ARCH_BOARD_STM32F429I_DISCO
source "boards/arm/stm32/stm32f429i-disco/Kconfig"
source "boards/arm/stm32f4/stm32f429i-disco/Kconfig"
endif
if ARCH_BOARD_STM32F4_DISCOVERY
source "boards/arm/stm32/stm32f4discovery/Kconfig"
source "boards/arm/stm32f4/stm32f4discovery/Kconfig"
endif
if ARCH_BOARD_STM32L_DISCOVERY
source "boards/arm/stm32/stm32ldiscovery/Kconfig"
source "boards/arm/stm32l1/stm32ldiscovery/Kconfig"
endif
if ARCH_BOARD_STM32VL_DISCOVERY
source "boards/arm/stm32/stm32vldiscovery/Kconfig"
source "boards/arm/stm32f1/stm32vldiscovery/Kconfig"
endif
if ARCH_BOARD_VIEWTOOL_STM32F107
source "boards/arm/stm32/viewtool-stm32f107/Kconfig"
source "boards/arm/stm32f1/viewtool-stm32f107/Kconfig"
endif
if ARCH_BOARD_OLIMEX_STRP711
source "boards/arm/str71x/olimex-strp711/Kconfig"

23
boards/arm/stm32/nucleo-f103rb/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f103rb/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f207zg/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f207zg/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

41
boards/arm/stm32/nucleo-f207zg/scripts/Make.defs
View file

@ -1,41 +0,0 @@
############################################################################
# boards/arm/stm32/nucleo-f207zg/scripts/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = ld.script
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

23
boards/arm/stm32/nucleo-f302r8/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f302r8/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

41
boards/arm/stm32/nucleo-f302r8/scripts/Make.defs
View file

@ -1,41 +0,0 @@
############################################################################
# boards/arm/stm32/nucleo-f302r8/scripts/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = ld.script
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

23
boards/arm/stm32/nucleo-f303re/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f303re/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f303ze/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f303ze/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f334r8/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f334r8/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

41
boards/arm/stm32/nucleo-f334r8/scripts/Make.defs
View file

@ -1,41 +0,0 @@
############################################################################
# boards/arm/stm32/nucleo-f334r8/scripts/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = ld.script
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

23
boards/arm/stm32/nucleo-f401re/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f401re/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f410rb/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f410rb/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f411re/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f411re/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f412zg/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f412zg/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f429zi/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f429zi/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-f446re/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-f446re/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-g431kb/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-g431kb/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-g431rb/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-g431rb/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/nucleo-g474re/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-g474re/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

51
boards/arm/stm32/nucleo-g474re/scripts/Make.defs
View file

@ -1,51 +0,0 @@
############################################################################
# boards/arm/stm32/nucleo-g474re/scripts/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
ifeq ($(CONFIG_STM32_DFU),y)
LDSCRIPT = ld.script.dfu
else
LDSCRIPT = ld.script
endif
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
# Embed absolute path to source file in debug information so that Eclipse
# source level debugging won't get confused. See:
# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information
CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..)

23
boards/arm/stm32/nucleo-l152re/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/nucleo-l152re/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

41
boards/arm/stm32/nucleo-l152re/scripts/Make.defs
View file

@ -1,41 +0,0 @@
############################################################################
# boards/arm/stm32/nucleo-l152re/scripts/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = ld.script
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

23
boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt
View file

@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

23
boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt
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@ -1,23 +0,0 @@
# ##############################################################################
# boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

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