diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index d6832ccd151..3528e51466d 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -962,20 +962,21 @@ arch/arm/include/samv7/samv71_irq.h alin.jerpelea@sony.com petro.karashchenko@gm arch/arm/include/setjmp.h david.s.alessio@gmail.com alin.jerpelea@sony.com guowei15@xiaomi.com xiaoxiang@xiaomi.com huangqi3@xiaomi.com arch/arm/include/spinlock.h alin.jerpelea@sony.com anchao.archer@bytedance.com xiaoxiang@xiaomi.com hujun5@xiaomi.com arch/arm/include/stdarg.h alin.jerpelea@sony.com guoshichao@xiaomi.com -arch/arm/include/stm32/chip.h raiden00pl@gmail.com 59230071+hartmannathan@users.noreply.github.com paul-a.patience@polymtl.ca -arch/arm/include/stm32/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me -arch/arm/include/stm32/stm32f10xxx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net -arch/arm/include/stm32/stm32f20xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f30xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f33xxx_irq.h 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f37xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com -arch/arm/include/stm32/stm32f40xxx_irq.h gwenj@trabucayre.com paul-a.patience@polymtl.ca david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32g4xxxx_irq.h raiden00@railab.me alin.jerpelea@sony.com devel@sumpfralle.de gustavo.nihei@espressif.com -arch/arm/include/stm32/stm32l15xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/include/stm32c0/chip.h raiden00@railab.me arch/arm/include/stm32c0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com arch/arm/include/stm32f0/chip.h raiden00@railab.me juha.niskanen@haltian.com dave@marples.net acassis@gmail.com arch/arm/include/stm32f0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com peter.barada@gmail.com +arch/arm/include/stm32f1/chip.h raiden00@railab.me +arch/arm/include/stm32f1/irq.h raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net peter.barada@gmail.com +arch/arm/include/stm32f2/chip.h raiden00@railab.me +arch/arm/include/stm32f2/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com +arch/arm/include/stm32f3/chip.h raiden00@railab.me +arch/arm/include/stm32f3/irq.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com mijung@gmx.net simon@leitwert.ch +arch/arm/include/stm32f3/stm32f30xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f3/stm32f33xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/include/stm32f3/stm32f37xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f4/chip.h raiden00@railab.me +arch/arm/include/stm32f4/irq.h david_s5@usa.net gwenj@trabucayre.com paul-a.patience@polymtl.ca alin.jerpelea@sony.com raiden00@railab.me arch/arm/include/stm32f7/chip.h david_s5@usa.net alin.jerpelea@sony.com bob.feretich@rafresearch.com dave@marples.net arch/arm/include/stm32f7/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com bob.feretich@rafresearch.com david_s5@usa.net arch/arm/include/stm32f7/stm32f72xx73xx_irq.h bob.feretich@rafresearch.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com @@ -983,6 +984,8 @@ arch/arm/include/stm32f7/stm32f74xx75xx_irq.h alin.jerpelea@sony.com 59230071+ha arch/arm/include/stm32f7/stm32f76xx77xx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com gustavo.nihei@espressif.com arch/arm/include/stm32g0/chip.h raiden00@railab.me arch/arm/include/stm32g0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/include/stm32g4/chip.h raiden00@railab.me +arch/arm/include/stm32g4/irq.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com devel@sumpfralle.de arch/arm/include/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/irq.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/stm32h5xx_irq.h kwilson@2g-eng.com alin.jerpelea@sony.com @@ -994,6 +997,8 @@ arch/arm/include/stm32h7/stm32h7x5xx_irq.h raiden00@railab.me alin.jerpelea@sony arch/arm/include/stm32h7/stm32h7x7xx_irq.h 59230071+hartmannathan@users.noreply.github.com lwazeh@gmail.com alin.jerpelea@sony.com gustavo.nihei@espressif.com arch/arm/include/stm32l0/chip.h raiden00@railab.me arch/arm/include/stm32l0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com 59230071+hartmannathan@users.noreply.github.com +arch/arm/include/stm32l1/chip.h raiden00@railab.me +arch/arm/include/stm32l1/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com arch/arm/include/stm32l4/chip.h juha.niskanen@haltian.com sebastien@lorquet.fr dave@marples.net alin.jerpelea@sony.com arch/arm/include/stm32l4/irq.h sebastien@lorquet.fr 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/include/stm32l4/stm32l4x3xx_irq.h juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com daniel.carvalho@ufu.br @@ -1550,6 +1555,342 @@ arch/arm/src/common/gnu/fork.S guoshichao@xiaomi.com yanghuatao@xiaomi.com liaoa arch/arm/src/common/hwcap.h liaoao@xiaomi.com alin.jerpelea@sony.com arch/arm/src/common/iar/arm_fetchadd.S xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/common/iar/fork.S guoshichao@xiaomi.com alin.jerpelea@sony.com +arch/arm/src/common/stm32/Kconfig raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.adc raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.ble raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.cache raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.can raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.comp raiden00@railab.me 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alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me +arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com konstantin@ansync.com raiden00pl@gmail.com raiden00@railab.me +arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com raiden00@railab.me raiden00pl@gmail.com paul-a.patience@polymtl.ca +arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h alin.jerpelea@sony.com raiden00@railab.me hartman.nathan@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h alin.jerpelea@sony.com raiden00@railab.me raiden00pl@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h alin.jerpelea@sony.com michal.lyszczek@gmail.com raiden00pl@gmail.com xiaoxiang@xiaomi.com raiden00@railab.me +arch/arm/src/stm32f1/stm32.h alin.jerpelea@sony.com raiden00@railab.me abdelatif.guettouche@gmail.com raiden00pl@gmail.com xiaoxiang@xiaomi.com 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-boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c acassis@gmail.com rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c rcsim10@gmail.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c acassis@gmail.com rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c rcsim10@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h rcsim10@gmail.com acassis@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f411-minimum/Kconfig michal.lyszczek@bofc.pl 101105604+simbit18@users.noreply.github.com tolstov_den@mail.ru acassis@gmail.com -boards/arm/stm32/stm32f411-minimum/Kconfig.gpio michal.lyszczek@bofc.pl -boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig tolstov_den@mail.ru acassis@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig acassis@gmail.com tolstov_den@mail.ru xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com liguiding1@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig samymtz66@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig samymtz66@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig tolstov_den@mail.ru acassis@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig tolstov_den@mail.ru acassis@gmail.com wangjianyu3@xiaomi.com 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buxiasen@xiaomi.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com anchao@xiaomi.com petro.karashchenko@gmail.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c alin.jerpelea@sony.com +boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com thomas.narayana-swamy@wandercraft.eu raiden00@railab.me boards/arm/stm32l0/b-l072z-lrwan1/Kconfig alin.jerpelea@sony.com boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com diff --git a/Documentation/applications/examples/ft80x/index.rst b/Documentation/applications/examples/ft80x/index.rst index 9020d67baf0..e093218737a 100644 --- a/Documentation/applications/examples/ft80x/index.rst +++ b/Documentation/applications/examples/ft80x/index.rst @@ -4,4 +4,4 @@ This examples has ports of several FTDI demos for the FTDI/BridgeTek FT80x GUI chip. As an example configuration, see -``nuttx/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig``. +``nuttx/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig``. diff --git a/Documentation/applications/system/usbmsc/index.rst b/Documentation/applications/system/usbmsc/index.rst index 57da5b30358..f387859f0ca 100644 --- a/Documentation/applications/system/usbmsc/index.rst +++ b/Documentation/applications/system/usbmsc/index.rst @@ -13,7 +13,7 @@ This function will be called by the ``system/usbmsc`` indirectly via the ``board block device drivers. For examples of the implementation of ``board_usbmsc_initialize()`` see ``boards/arm/lpc214x/mcu123-lpc214x/src/up_usbmsc.c`` or -``boards/arm/stm32/stm3210e-eval/src/usbmsc.c``. +``boards/arm/stm32f1/stm3210e-eval/src/usbmsc.c``. Configuration options: diff --git a/Documentation/components/drivers/character/leds/userled.rst b/Documentation/components/drivers/character/leds/userled.rst index dd8ae215ccb..feccbcb4c7d 100644 --- a/Documentation/components/drivers/character/leds/userled.rst +++ b/Documentation/components/drivers/character/leds/userled.rst @@ -59,7 +59,7 @@ Files supporting USERLED can be found in the following locations: Something important to note is that your board initialization code (normally named ``_bringup.c`` should call the function to register the driver. -For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: +For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: .. code-block:: C diff --git a/Documentation/components/drivers/character/serial.rst b/Documentation/components/drivers/character/serial.rst index 7af619f1270..52b099e6da1 100644 --- a/Documentation/components/drivers/character/serial.rst +++ b/Documentation/components/drivers/character/serial.rst @@ -39,7 +39,7 @@ Serial Device Drivers `character drivers <#chardrivers>`__ and are accessed as other character drivers. -- **Examples**: ``arch/arm/src/stm32/stm32_serial.c``, +- **Examples**: ``arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c``, ``arch/arm/src/lpc214x/lpc214x_serial.c``, ``arch/z16/src/z16f/z16f_serial.c``, etc. diff --git a/Documentation/components/drivers/special/lcd.rst b/Documentation/components/drivers/special/lcd.rst index 3e415e19694..5417a2a1bb9 100644 --- a/Documentation/components/drivers/special/lcd.rst +++ b/Documentation/components/drivers/special/lcd.rst @@ -85,7 +85,7 @@ LCDs Generic LCD driver for LCDs based on the Solomon Systech SSD1289 LCD controller. Think of this as a template for an LCD driver that you will probably have to customize for any particular LCD - hardware. (See also boards/arm/stm32/hymini-stm32v/src/ssd1289.c below). + hardware. (See also boards/arm/stm32f1/hymini-stm32v/src/ssd1289.c below). - ``st7567.c`` @@ -120,7 +120,7 @@ OLEDs OLED Display Module, UUG-2864AMBAG01, Univision Technology Inc. Based on the SH1101A controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/lpc214x/zp214xpa - ``ug-9664hswag01.c`` @@ -140,7 +140,7 @@ OLEDs Densitron Technologies DD-12864WO-4A which is based on SSD1309 LCD controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/sam34/sam4l-xplained Segment LCDS (SLCDs) diff --git a/Documentation/components/drivers/special/sdio.rst b/Documentation/components/drivers/special/sdio.rst index 6822b82d388..ba62f204957 100644 --- a/Documentation/components/drivers/special/sdio.rst +++ b/Documentation/components/drivers/special/sdio.rst @@ -29,7 +29,7 @@ SDIO Device Drivers #. Provide that instance to the initialization method of the higher level device driver. -- **Examples**: ``arch/arm/src/stm32/stm32_sdio.c`` and +- **Examples**: ``arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c`` and ``drivers/mmcsd/mmcsd_sdio.c`` Implementing an SDIO lower-half diff --git a/Documentation/components/drivers/special/usbdev.rst b/Documentation/components/drivers/special/usbdev.rst index 589a60b7b7f..1b83d9a20d7 100644 --- a/Documentation/components/drivers/special/usbdev.rst +++ b/Documentation/components/drivers/special/usbdev.rst @@ -19,7 +19,7 @@ USB Device-Side Drivers ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c``, ``arch/arm/src/lpc214x/lpc214x_usbdev.c``, ``arch/arm/src/lpc313x/lpc313x_usbdev.c``, and - ``arch/arm/src/stm32/stm32_usbdev.c``. + ``arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c``. - ``struct usbdevclass_driver_s``. Each USB device class driver must implement an instance of diff --git a/Documentation/components/drivers/special/usbhost.rst b/Documentation/components/drivers/special/usbhost.rst index 63077758d10..078677d5e29 100644 --- a/Documentation/components/drivers/special/usbhost.rst +++ b/Documentation/components/drivers/special/usbhost.rst @@ -17,7 +17,7 @@ USB Host-Side Drivers **Examples**: ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c``, - ``arch/arm/src/stm32/stm32_otgfshost.c``, + ``arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c``, ``arch/arm/src/sama5/sam_ohci.c``, and ``arch/arm/src/sama5/sam_ehci.c``. diff --git a/Documentation/contributing/making-changes.rst b/Documentation/contributing/making-changes.rst index a60182210b4..7cbe6cb0add 100644 --- a/Documentation/contributing/making-changes.rst +++ b/Documentation/contributing/making-changes.rst @@ -227,7 +227,7 @@ squash before submitting the Pull Request: .. code-block:: bash - arch/arm/stm32/: Add arch support for stm32 platform + arch/arm/stm32f4/: Add arch support for stm32f4 platform This patch adds initial support for stm32 platform. Please read the documentation included for more details how to wire the display. diff --git a/Documentation/guides/changing_systemclockconfig.rst b/Documentation/guides/changing_systemclockconfig.rst index 872415486eb..0b5039ee2ce 100644 --- a/Documentation/guides/changing_systemclockconfig.rst +++ b/Documentation/guides/changing_systemclockconfig.rst @@ -28,7 +28,7 @@ Custom Clock Configuration The ``configs/vsn/`` configuration does something like you say. It skips the initial clock configuration by defining ``CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y``. Then the normal clock -configuration logic in ``arch/arm/src/stm32/stm32_rcc.c`` is not executed. +configuration logic in ``arch/arm/src/stm32f4/stm32_rcc.c`` is not executed. Instead, the "custom" clock initialization at ``configs/vsn/src/sysclock.c`` is called: @@ -83,7 +83,7 @@ are hardcoded in the board.h header file. So you have two options: 2. **Variable Peripheral Clocking**. You can make the peripheral clocking variable. I had to do this for the SAMA5Dx family. Look at - ``boards/arm/stm32/sama5d4-ek/include/board_sdram.h`` for example. Notice + ``boards/arm/sama5/sama5d4-ek/include/board_sdram.h`` for example. Notice that the frequencies are not constants, but function calls: .. code-block:: c diff --git a/Documentation/guides/etcromfs.rst b/Documentation/guides/etcromfs.rst index 8bc92ef989e..39ce17bddd2 100644 --- a/Documentation/guides/etcromfs.rst +++ b/Documentation/guides/etcromfs.rst @@ -86,7 +86,7 @@ behave as follows at Nuttx start-up time: ``CONFIG_ETC_ROMFS=y`` in the NuttX configuration file. They might provide useful examples: - - ``boards/arm/stm32/hymini-stm32v/nsh2`` + - ``boards/arm/stm32f1/hymini-stm32v/nsh2`` - ``boards/arm/dm320/ntosd-dm320/nsh`` - ``boards/sim/sim/sim/nsh`` - ``boards/sim/sim/sim/nsh2`` diff --git a/Documentation/guides/ipv6.rst b/Documentation/guides/ipv6.rst index d67c30c5189..bf02bc57f81 100644 --- a/Documentation/guides/ipv6.rst +++ b/Documentation/guides/ipv6.rst @@ -218,7 +218,7 @@ Board Configurations At present, there are three board configuration that are pre-configured to use IPv6: ``nuttx/boards/arm/tiva/dk-tm4c129x/configs/ipv6``, -``nuttx/boards/arm/stm32/stm32f4discovery/ipv6``, and +``nuttx/boards/arm/stm32f4/stm32f4discovery/ipv6``, and ``nuttx/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6``. These default configurations have only IPv6 enabled. But the `README` files at in those board directories describes how to enable `both` IPv4 and IPv6 simultaneously. @@ -345,4 +345,4 @@ the network utils (``netutils``). * Netutils: The network utilities in ``apps/netutils`` have been adapted to work with IPv6: DHCP, FTP, TFTP, Telnet, etc. Support for managing IPv6 address have been included in the ``netlib``, but nothing else has yet been - updated. \ No newline at end of file + updated. diff --git a/Documentation/guides/nsh_network_link_management.rst b/Documentation/guides/nsh_network_link_management.rst index 3100f7ba7d8..05cc4f9d419 100644 --- a/Documentation/guides/nsh_network_link_management.rst +++ b/Documentation/guides/nsh_network_link_management.rst @@ -45,7 +45,7 @@ must be satisfied: are implemented for Atmel SAM4/4, SAMA5 families, and for the STMicro STM32. See ``nuttx/arch/arm/src/sam34/sam_emac.c``, ``nuttx/arch/arm/src/sam34/sam_emaca.c``, ``sam_emacb.c``, and ``sam_gmac.c``, - and ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + and ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. - ``CONFIG_ARCH_PHY_INTERRUPT`` This is not a user-selectable option. Rather, it is set when selecting a board that supports PHY interrupts. In most architectures, the PHY interrupt is not diff --git a/Documentation/guides/ofloader.rst b/Documentation/guides/ofloader.rst index 743fb9d1328..4dfe2375dc9 100644 --- a/Documentation/guides/ofloader.rst +++ b/Documentation/guides/ofloader.rst @@ -52,7 +52,7 @@ Precautions 1.If you need to implement the ofloader on a different board, you will need to read the `wiki ` and refer to the implementation of "ofloader.ld" linker script located -in the "boards/arm/stm32/stm32f429i-disco/scripts" directory. +in the "boards/arm/stm32f4/stm32f429i-disco/scripts" directory. This linker script defines how the different sections of the NuttX image are placed in memory. You should configure the corresponding sections to be located in RAM, where the J-Link can write the image correctly. diff --git a/Documentation/guides/partially_linked_elf.rst b/Documentation/guides/partially_linked_elf.rst index 0fe721e69ed..b2b6ee8f307 100644 --- a/Documentation/guides/partially_linked_elf.rst +++ b/Documentation/guides/partially_linked_elf.rst @@ -40,7 +40,7 @@ compatible with the example provided here: In this example, let's illustrate this using an STM32F4-Discovery configuration. We will assume that you have modified the - ``boards/arm/stm32/stm32fdiscovery/src/stm32_bringup.c`` file, adding the + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` file, adding the following: .. code-block:: c diff --git a/Documentation/guides/port_drivers_to_stm32f7.rst b/Documentation/guides/port_drivers_to_stm32f7.rst index e7c04a2f3e3..876d184242f 100644 --- a/Documentation/guides/port_drivers_to_stm32f7.rst +++ b/Documentation/guides/port_drivers_to_stm32f7.rst @@ -191,7 +191,7 @@ An Example There is a good example in the STM32 Ethernet driver. The STM32 F7 Ethernet driver (``arch/arm/src/stm32f7/stm32_ethernet.c``) derives directly from the STM32 F4 Ethernet driver -(``arch/arm/src/stm32/stm32_eth.c``). These two Ethernet MAC peripherals +(``arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``). These two Ethernet MAC peripherals are nearly identical. Only changes that are a direct consequence of the STM32 F7 D-Cache were required to make the driver work on the STM32 F7. Those changes are summarized below. diff --git a/Documentation/guides/protected_build.rst b/Documentation/guides/protected_build.rst index e2a60713a3a..a49702df5c7 100644 --- a/Documentation/guides/protected_build.rst +++ b/Documentation/guides/protected_build.rst @@ -177,10 +177,10 @@ Files and Directories Here is a summary of directories and files used by the STM32F4Discovery protected build: -* ``boards/arm/stm32/stm32f4discovery/configs/kostest``. This is the kernel +* ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. This is the kernel mode OS test configuration. The two standard configuration files can be found in this directory: (1) ``defconfig`` and (2) ``Make.defs``. -* ``boards/arm/stm32/stm32f4discovery/kernel``. This is the first past +* ``boards/arm/stm32f4/stm32f4discovery/kernel``. This is the first past build directory. The Makefile in this directory is invoked to produce the pass1 object (``nuttx_user.elf`` in this case). The second pass object is created by ``arch/arm/src/Makefile``. Also @@ -188,7 +188,7 @@ protected build: contains a header that includes information need by the kernel blob in order to interface with the user-code. That header is defined in by this file. -* ``boards/arm/stm32/stm32f4discovery/scripts``. Linker scripts for +* ``boards/arm/stm32f4/stm32f4discovery/scripts``. Linker scripts for the kernel mode build are found in this directory. This includes (1) ``memory.ld`` which hold the common memory map, (2) ``user-space.ld`` that is used for linking the pass1 user-mode blob, and (3) @@ -314,11 +314,11 @@ Comparing the "Flat" Build Configuration with the Protected Build Configuration =============================================================================== Compare, for example the configuration -``boards/arm/stm32/stm32f4discovery/configs/ostest`` and the -configuration ``boards/arm/stm32/stm32f4discovery/configs/kostest``. +``boards/arm/stm32f4/stm32f4discovery/configs/ostest`` and the +configuration ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. These two configurations are identical except that one builds a "flat" version of OS test and the other builds a kernel version -of the OS test. See the file ``boards/arm/stm32/stm32f4discovery/README.txt`` +of the OS test. See the file ``boards/arm/stm32f4/stm32f4discovery/README.txt`` for more details about those configurations. The configurations can be compared using the ``cmpconfig`` tool: @@ -328,7 +328,7 @@ The configurations can be compared using the ``cmpconfig`` tool: cd tools make -f Makefile.host cmpconfig cd .. - tools/cmpconfig boards/arm/stm32/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig + tools/cmpconfig boards/arm/stm32f4/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig Here is a summary of the meaning of all of the important differences in the configurations. This should be enough information for you to convert any @@ -337,7 +337,7 @@ configuration from a "flat" to a protected build: * ``CONFIG_BUILD_2PASS=y``. This enables the two pass build. * ``CONFIG_BUILD_PROTECTED=y``. This option enables the "two pass" protected build. -* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel"``. +* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel"``. This tells the build system the (relative) location of the pass1 build directory. * ``CONFIG_PASS1_OBJECT=""``. In some "two pass" build configurations, the build system need to know the name of the first pass object. @@ -382,7 +382,7 @@ configuration from a "flat" to a protected build: These includes such things as initializing device drivers. These same initialization steps must be performed in kernel mode for the protected build and ``CONFIG_BOARD_LATE_INITIALIZE``. - See ``boards/arm/stm32/stm32f4discovery/src/up_boot.c`` for an + See ``boards/arm/stm32f4/stm32f4discovery/src/up_boot.c`` for an example of such board initialization code. Architecture-Specific Options: @@ -409,8 +409,8 @@ Size Expansion The protected build will, or course, result in a FLASH image that is larger than that of the corresponding "flat" build. How much larger? I don't have the numbers in hand, but you can build -``boards/arm/stm32/stm32f4discovery/configs/nsh`` and -``boards/arm/stm32/stm32f4discovery/configs/kostest`` and compare +``boards/arm/stm32f4/stm32f4discovery/configs/nsh`` and +``boards/arm/stm32f4/stm32f4discovery/configs/kostest`` and compare the resulting binaries for yourself using the ``size`` command. Increases in size are expected because: diff --git a/Documentation/guides/smaller_vector_tables.rst b/Documentation/guides/smaller_vector_tables.rst index 2cc629fa2a5..ed44b0432d2 100644 --- a/Documentation/guides/smaller_vector_tables.rst +++ b/Documentation/guides/smaller_vector_tables.rst @@ -202,7 +202,7 @@ Most ARMv7-M architectures support two mechanism for handling interrupts: ``CONFIG_ARMV7M_CMNVECTOR=y`` that can be found in ``arch/arm/src/armv7-m/``, and * MCU-specific interrupt handling logic. For the - STM32, this logic can be found at ``arch/arm/src/stm32/gnu/stm32_vectors.S``. + STM32, this logic can be found at ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``. The `common` vector logic is slightly more efficient, the MCU-specific logic is slightly more flexible. @@ -229,7 +229,7 @@ This technical approach requires changes to three files: define ``only`` the small set of 20 ``mapped`` IRQ numbers in the range from 0 through 19. It would also set ``NR_IRQS`` to the value 20. -* A new header file at ``arch/arm/src/stm32/hardware``, say +* A new header file at ``arch/arm/src/stm32f4/hardware``, say ``xyz_vector.h``. It would be similar to the other vector definitions files in that directory: It will consist of a sequence of 100 ``VECTOR`` and ``UNUSED`` macros. It will @@ -248,7 +248,7 @@ This has all been replaced with the common vector handling at Vector Definitions ================== -In ``arch/arm/src/stm32/gnu/stm32_vector.S``, notice that the +In ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``, notice that the ``xyz_vector.h`` file will be included twice. Before each inclusion, the macros ``VECTOR`` and ``UNUSED`` are defined. @@ -290,7 +290,7 @@ file like this: ... Where the value of ``STM32_IRQ_USART1`` was defined to -be 12 in the ``arch/arm/include/stm32/xyz_irq.h`` header +be 12 in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file. When ``xyz_vector.h`` is included by ``stm32_vectors.S`` with the above definitions for ``VECTOR`` and ``UNUSED``, the following would result: @@ -349,7 +349,7 @@ second time the ``xzy_vector.h`` is included by ``stm32_vectors.S``: In the above USART1 example, a single handler would be generated that will provide the IRQ number 12. Remember that 12 is the expansion of the macro ``STM32_IRQ_USART1`` -that is provided in the ``arch/arm/include/stm32/xyz_irq.h`` +that is provided in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file: .. code-block:: asm diff --git a/Documentation/guides/stm32ccm.rst b/Documentation/guides/stm32ccm.rst index 4ec8ba5acb3..14148131805 100644 --- a/Documentation/guides/stm32ccm.rst +++ b/Documentation/guides/stm32ccm.rst @@ -34,7 +34,7 @@ This memory allocator is automatically enabled when the following options are se * ``CONFIG_MM_MULTIHEAP`` Support for multiple heaps is enabled. Under those conditions, the CCM memory allocator is enabled and the allocator -interfaces prototyped in the ``arch/arm/src/stm32/stm32_ccm.h`` are available. +interfaces prototyped in the ``arch/arm/src/common/stm32/stm32_ccm.h`` are available. NOTE: These interfaces are, technically, not prototyped since they are really provided via C pre-processor macros. diff --git a/Documentation/guides/usingkernelthreads.rst b/Documentation/guides/usingkernelthreads.rst index 5818842037a..434dacd62a0 100644 --- a/Documentation/guides/usingkernelthreads.rst +++ b/Documentation/guides/usingkernelthreads.rst @@ -52,7 +52,7 @@ In order to build the task into the OS as a kernel thread, you simply have to: (1) place the kernel thread code in your board source code directory, and (2) start it with ``kthread_create()`` in your board bring-up logic. There a few examples of this in the NuttX source tree. Here is one: -`https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c `_ +`https://github.com/apache/nuttx/blob/master/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c `_ So that is another trick that you can use to architecture optimal solutions: Create parts of your applications as kernel threads: They need to reside in diff --git a/Documentation/guides/zerolatencyinterrupts.rst b/Documentation/guides/zerolatencyinterrupts.rst index 7acd9352656..2a5f14e70c2 100644 --- a/Documentation/guides/zerolatencyinterrupts.rst +++ b/Documentation/guides/zerolatencyinterrupts.rst @@ -302,8 +302,8 @@ You can find an example that tests the high priority, nested interrupts in the N * :doc:`/platforms/arm/stm32f1/boards/viewtool-stm32f107/index` Description of the configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/highpri`` Test configuration +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/highpri`` Test configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri`` Test +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri`` Test driver. diff --git a/Documentation/implementation/chip_h.rst b/Documentation/implementation/chip_h.rst index a2b71584126..2a9d9641986 100644 --- a/Documentation/implementation/chip_h.rst +++ b/Documentation/implementation/chip_h.rst @@ -12,16 +12,16 @@ If you wonder about the purpose of the two ``chip.h`` files in each arm chip. .. code:: sh $ find arch/arm -name chip.h | grep stm32 - arch/arm/include/stm32/chip.h - arch/arm/src/stm32/chip.h + arch/arm/include/stm32f4/chip.h + arch/arm/src/stm32f4/chip.h -The reason behind ``arch/arm/src/stm32/chip.h`` file was a bad idea +The reason behind ``arch/arm/src/stm32f4/chip.h`` file was a bad idea that happened a long time ago. Right now, I believe that its only required when ``CONFIG_ARMV7M_CMNVECTOR`` -is selected in the configuration. In that case, ``arch/arm/src/stm32/chip.h`` +is selected in the configuration. In that case, ``arch/arm/src/stm32f4/chip.h`` is included by ``arch/arm/src/armv7-m/up_vectors.c`` in order provide -the number of interrupt vectors. In stm32, ``arch/arm/src/stm32/chip.h`` +the number of interrupt vectors. In stm32, ``arch/arm/src/stm32f4/chip.h`` provides the number of vectors indirectly by including the correct, chip-specific vectors.h file. This function is a little more obvious in ``arch/arm/srch/lpc43xx/chip.h``. diff --git a/Documentation/implementation/file_descriptors.rst b/Documentation/implementation/file_descriptors.rst index dfad984a347..a54ffae2f04 100644 --- a/Documentation/implementation/file_descriptors.rst +++ b/Documentation/implementation/file_descriptors.rst @@ -135,7 +135,7 @@ Detached File Helpers Once the file structure has been detached from its file descriptor, you can no longer use the standard VFS functions ``read()``, ``write()``, ``ioctl()``, etc. Fortunately, there are a parallel set of interfaces -that can be used with detached files. These are decribed in detail +that can be used with detached files. These are described in detail in ``include/nuttx/fs/fs.h`` and only listed here below: .. code-block:: c @@ -153,8 +153,8 @@ in ``include/nuttx/fs/fs.h`` and only listed here below: int file_vfcntl(FAR struct file *filep, int cmd, va_list ap); -The SYLOG Device: A Case Study -============================== +The SYSLOG Device: A Case Study +=============================== This technique is used for the SYSLOG device. Originally, NuttX used file descriptor ``1`` for SYSLOG output by default. For most task groups, @@ -179,7 +179,7 @@ Other Examples There are some other examples in analog joystick lower half drivers that use the ADC character driver to read joystick positions:: - boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c: + boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c: ret = file_detach(fd, &g_adcfile); boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c: diff --git a/Documentation/implementation/nuttx_initialization_sequence.rst b/Documentation/implementation/nuttx_initialization_sequence.rst index 2538e7d3a4b..0c68e50e715 100644 --- a/Documentation/implementation/nuttx_initialization_sequence.rst +++ b/Documentation/implementation/nuttx_initialization_sequence.rst @@ -35,7 +35,7 @@ to any supported architecture. Here is the map of initialization function calls:: - __start()-arch/arm/src/stm32/stm32_start.c + __start()-arch/arm/src/common/stm32/stm32_start_m3m4_v1.c | +--*Set stack limit +--stm32_clockconfig() @@ -45,7 +45,7 @@ Here is the map of initialization function calls:: +--showprogress('A') +-- +-- - +--stm32_boardinitialize()-boards/arm/stm32/stm32f4discovery/src/stm32_boot.c + +--stm32_boardinitialize()-boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c | | | +--stm32_spidev_initialize()-stm32_spi.c:ONLY CHIP SELECTS | +--stm32_usbinitialize()- @@ -196,7 +196,7 @@ There are few important things to note about this file. ``.section .vectors, ax``. This pseudo operation will place all of the vectors into a special section call ``.vectors``. On of the STM32 F4 linker scripts is located at -``nuttx/boards/arm/stm32/stm32f4discovery/scripts/ld.script``. +``nuttx/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script``. In that file, you can see that section ``.vectors`` is forced to lie at the very beginning of FLASH memory. The STM32 F4 can be configured to boot in different ways via strapping. @@ -229,7 +229,7 @@ nuttx/arch/arm/src/stm32_start.c ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The reset vector ``__start`` lies in the file -``nuttx/arch/arm/src/stm32/stm32_start.c`` and does the real, +``nuttx/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c`` and does the real, low-level architecture-specific initialization. This initialization includes: 1. ``stm32_clockconfig()`` - Initialize the PLLs and peripheral clocking @@ -262,7 +262,7 @@ low-level architecture-specific initialization. This initialization includes: 7. ``stm32_boardinitialize()`` - Board-specific logic is initialized by calling this function. For the case of the STM32F4Discovery board, this logic can be found at - ``nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c`` and does + ``nuttx/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c`` and does the following operations: a. ``stm32_spidev_initialize()`` - Initialize SPI chip selects @@ -351,19 +351,19 @@ file and in that case those operations are not performed: ``nx_start()``. However, if the board supports multiple, discontiguous memory regions, any addition memory regions can be added to the heap by this function. For the STM32 F4, ``up_addregion()`` is implemented - in ``nuttx/arch/arm/src/stm32/stm32_allocateheap.c``. + in ``nuttx/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c``. * ``arm_pminitialize()`` - If ``CONFIG_PM`` is defined, the function must initialize the power management subsystem. This MCU-specific function - must be called very early in the intialization sequence before any other + must be called very early in the initialization sequence before any other device drivers are initialized (since they may attempt to register with the power management subsystem). There is no implementation of ``up_pminitialize()`` for any STM32 platform. * ``arm_dmainitialize()`` - Initialize the DMA subsystem. For the STM32 F4, this DMA initialization can be found in - ``nuttx/arch/arm/src/stm32/stm32_dma.c`` (which includes - ``nuttx/arch/arm/src/stm32f4xxx_dma.c``). + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c`` (which includes + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c``). * ``devnull_register()`` - Registers the standard ``/dev/null``. @@ -381,11 +381,11 @@ file and in that case those operations are not performed: (found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c`` STM32 F4). * ``arm_netinitialize()`` - Initialize the network. For the STM32 F4, - this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + this function is in ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. * ``arm_usbinitialize()`` - Initialize USB (host or device). For the STM32 F4, this function is in - ``nuttx/arch/arm/src/stm32/stm32_otgfsdev.c``. + ``nuttx/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c``. * ``arm_l2ccinitialize()`` - Initialize the L2 cache if present and selected. @@ -448,7 +448,7 @@ This function performed the following specific operations: for a variety of purposes like misc garbage clean-up. * ``nx_create_initthread()`` - Once the operating system has been initialized, - this funcions either directly calls ``nx_start_application()`` or creates + this functions either directly calls ``nx_start_application()`` or creates a thread for running it * ``nx_start_application()`` - If set in the NuttX configuration, @@ -640,7 +640,7 @@ The resulting ROMFS file system can be found in * ``board_app_initialize()`` - For the STM32F4Discovery, this architecture specific initialization can be found at - ``boards/arm/stm32/stm32f4discovery/src/stm32_appinit.c``. + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_appinit.c``. This it does things like: 1. Initialize SPI devices. diff --git a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst index 19ce66c3fb0..9c15d336c5d 100644 --- a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst @@ -228,13 +228,13 @@ OpenOCD ======= I have also used OpenOCD with the M3 Wildfire. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/fire-stm32v2/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/fire-stm32v2/tools/oocd.sh $PWD + boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh $PWD - Load NuttX:: diff --git a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst index d544bea76b2..14f2d03a4cd 100644 --- a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst @@ -517,7 +517,7 @@ NOTES: ADC_IN8 (PB0) CON5 CN14 Pin2 ADC_IN9 (PB1) CON5 CN14 Pin1 - The signal selection is hard-coded in boards/arm/stm32/shenzhou/src/up_adc.c: The + The signal selection is hard-coded in boards/arm/stm32f1/shenzhou/src/up_adc.c: The potentiometer input (only) is selected. These selections will enable sampling the potentiometer input at 100Hz using diff --git a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst index fb218ff3c3b..3e499fbfe9b 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst @@ -87,13 +87,13 @@ OpenOCD ======= I have also used OpenOCD with the STM3210E-EVAL. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/stm3210e-eval/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/stm3210e-eval/tools/oocd.sh $PWD + boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh $PWD - Load NuttX:: @@ -171,7 +171,7 @@ More complex temperature sensor operations are also available. See the IOCTL commands enumerated in include/nuttx/sensors/lm75.h. Also read the descriptions of the stm32_lm75initialize() and stm32_lm75attach() interfaces in the arch/board/board.h file (sames as -boards/arm/stm32/stm3210e-eval/include/board.h). +boards/arm/stm32f1/stm3210e-eval/include/board.h). NSH Command Line Application ---------------------------- @@ -812,7 +812,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -824,8 +824,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 4. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst index 68819f0f603..e818cabd221 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst @@ -186,7 +186,7 @@ instead of 64KiB as documented in the datasheet and reported by its internal register. In order to enable 128KiB you need modify the linker script to reflect this -new size. Open the boards/arm/stm32/stm32f103-minimum/scripts/ld.script and replace:: +new size. Open the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script and replace:: flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K @@ -358,7 +358,7 @@ enable/disable these options using "make menuconfig" :: Memory Management ---> [*] Small memory model - Also change the boards/arm/stm32/stm32f103-minimum/scripts/ld.script file to use 128KB + Also change the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script file to use 128KB of Flash instead 64KB (since this board has a hidden 64KB flash) : MEMORY diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst index 8e76e5abc8c..81c6d7b8289 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst @@ -12,7 +12,7 @@ LEDs It is assumed that STMicro STM32F100RB generic board board has one LED on PA0. You should configure the port and pin number in -boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by +boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the board port is defined in include/board.h and src/up_leds.c. The LED is used to encode OS-related events as follows:: diff --git a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst index 40be36a0576..b2584194578 100644 --- a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst @@ -79,7 +79,7 @@ Using JTAG The Clicker2 comes with the mikroBootloader installed. That bootloader has not been used and is possibly incompatible with the Clicker2-STM32 -linker script at boards/arm/stm32/clicker2-stm32/scripts/flash.ld. Often code must +linker script at boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld. Often code must be built to execute at an offset in to FLASH when a bootloader is used. Certainly that is the case for the ST-Micro DFU bootloader but I am not aware of the requirements for use with the mikroBootloader. diff --git a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst index 7021a333f0e..e81cd71ba97 100644 --- a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst @@ -79,6 +79,6 @@ package as flexible as, say, an STM32F4 Discovery board. Build Instructions ================== -The boards/arm/stm32/omnibusf4/nsh/defconfig file creates a basic setup, and +The boards/arm/stm32f4/omnibusf4/nsh/defconfig file creates a basic setup, and includes drivers for all supported onboard chips. The console and command prompt are sent to USART3. diff --git a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst index 65a7eaf7831..ea78006fcfd 100644 --- a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst @@ -517,7 +517,7 @@ MAPPING TO STM32 F4:: 4 Also the reset pin for the CS43L22 audio Codec. NOTE: The configuration to test this LCD configuration is available at -boards/arm/stm32/stm32f4discovery/nxlines. As of this writing, I have not seen the +boards/arm/stm32f4/stm32f4discovery/nxlines. As of this writing, I have not seen the LCD working so I probably have some things wrong. I might need to use a bit-banging interface. Below is the pin configuration @@ -613,7 +613,7 @@ that I am using:: Darcy Gong recently added support for the UG-2864HSWEG01 OLED which is also an option with this configuration. I have little technical information about -the UG-2864HSWEG01 interface (see boards/arm/stm32/stm32f4discovery/src/up_ug2864hsweg01.c). +the UG-2864HSWEG01 interface (see boards/arm/stm32f4/stm32f4discovery/src/up_ug2864hsweg01.c). NiceRF LoRa (2AD66-LoRa V2) =========================== @@ -639,7 +639,7 @@ connect the CS to PA4, connect RST to PE1 and finally connect INT to PE4. The next step is to enable the ENC28J60 in the menuconfig ("make menuconfig") and the necessary Network configuration, you can use the -boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig as reference. +boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig as reference. HCI UART ======== @@ -1202,7 +1202,7 @@ NOTES: The HCI UART selection can be changed by re-configuring and assigning the different U[S]ART to the HCI. The U[S]ART pin selections can be changed by modifying the disambiguation definitions in -boards/arm/stm32/stm32f4discovery/include/board.h +boards/arm/stm32f4/stm32f4discovery/include/board.h I have been testing with the DVK_BT960_SA board via J10 as follows:: @@ -2021,7 +2021,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -2033,8 +2033,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 3. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f4/index.rst b/Documentation/platforms/arm/stm32f4/index.rst index 3684b7dd5a0..474dae92be6 100644 --- a/Documentation/platforms/arm/stm32f4/index.rst +++ b/Documentation/platforms/arm/stm32f4/index.rst @@ -389,7 +389,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst index 578ca414e57..0c691673f2a 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst @@ -106,7 +106,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst index 17cb93b0dcc..914494906fa 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst @@ -107,7 +107,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/quickstart/organization.rst b/Documentation/quickstart/organization.rst index 006444feb8e..af0cb591ebe 100644 --- a/Documentation/quickstart/organization.rst +++ b/Documentation/quickstart/organization.rst @@ -68,7 +68,7 @@ specified by several settings in the NuttX configuration file. sub-directories and are discussed in a paragraph `below <#boards-subdirectory-structure>`__. - The directory ``boards/arm/stm32/stm32f4disovery/``, as an + The directory ``boards/arm/stm32f4/stm32f4discovery/``, as an example, holds board-specific logic for the STM32F4 Discovery board and is selected via the ``CONFIG_ARCH_BOARD="stm32f4discovery"`` configuration setting. diff --git a/LICENSE b/LICENSE index a76c658ae4e..a22fd18f559 100644 --- a/LICENSE +++ b/LICENSE @@ -2918,7 +2918,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/photon/src/stm32_wlan_firmware.c +boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h ================================================ @@ -3249,8 +3249,8 @@ ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. boards/arm/rp2040/common/src/rp2040_ina219.c -boards/arm/stm32/common/src/stm32_ina219.c -boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c +boards/arm/common/stm32/src/stm32_ina219.c +boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c =============================================== Copyright (C) 2018,2019 Erle Robotics (Juan Flores Muñoz). All rights reserved. @@ -3282,9 +3282,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f303re/src/stm32_uid.c -boards/arm/stm32/omnibusf4/src/stm32_uid.c -boards/arm/stm32/stm32f4discovery/src/stm32_uid.c +boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c +boards/arm/stm32f4/omnibusf4/src/stm32_uid.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c boards/arm/stm32h7/nucleo-h743zi/src/stm32_uid.c boards/arm/stm32h7/stm32h747i-disco/src/stm32_uid.c =============================================== @@ -3317,8 +3317,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c -boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c +boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c ================================================= Copyright (C) 2017 Gregory Nutt. All rights reserved. Copyright (C) 2017 Brian Webb. All rights reserved. @@ -3350,10 +3350,10 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/omnibusf4/src/stm32_romfs.h -boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c -boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h -boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c +boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h +boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c boards/arm/stm32f7/common/include/stm32_romfs.h boards/arm/stm32f7/common/src/stm32_romfs_initialize.c ============================================================= @@ -3975,7 +3975,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f100_pinmap.h +arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h ================================================= Copyright (C) 2009 Gregory Nutt. All rights reserved. @@ -4009,7 +4009,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h +arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h ==================================================== Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. @@ -4042,7 +4042,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_alt.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c =================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4076,7 +4076,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_v2.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c =========================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4110,8 +4110,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_sdadc.c -arch/arm/src/stm32/stm32_sdadc.h +arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c +arch/arm/src/common/stm32/stm32_sdadc.h =================================== Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. @@ -4144,7 +4144,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tickless.c +arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c ====================================== Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. @@ -4177,7 +4177,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tim_lowerhalf.c +arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c =========================================== Copyright (C) 2015 Wail Khemir. All rights reserved. @@ -4210,8 +4210,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_uid.c -arch/arm/src/stm32/stm32_uid.h +arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c +arch/arm/src/common/stm32/stm32_uid.h =================================== Copyright (C) 2015 Marawan Ragab. All rights reserved. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 603dab1a965..e45eed4a24e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1317,8 +1317,16 @@ config ARCH_CHIP default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 - default "stm32" if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default "stm32f1" if ARCH_CHIP_STM32F1 + default "stm32f2" if ARCH_CHIP_STM32F2 + default "stm32f3" if ARCH_CHIP_STM32F3 + default "stm32f4" if ARCH_CHIP_STM32F4 + default "stm32g4" if ARCH_CHIP_STM32G4 + default "stm32l1" if ARCH_CHIP_STM32L1 + default "stm32f0" if ARCH_CHIP_STM32F0 + default "stm32l0" if ARCH_CHIP_STM32L0 + default "stm32g0" if ARCH_CHIP_STM32G0 + default "stm32c0" if ARCH_CHIP_STM32C0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 @@ -1819,11 +1827,35 @@ endif if ARCH_CHIP_SAMV7 source "arch/arm/src/samv7/Kconfig" endif -if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 -source "arch/arm/src/stm32/Kconfig" +if ARCH_CHIP_STM32F1 +source "arch/arm/src/stm32f1/Kconfig" endif -if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 -source "arch/arm/src/stm32f0l0g0/Kconfig" +if ARCH_CHIP_STM32F2 +source "arch/arm/src/stm32f2/Kconfig" +endif +if ARCH_CHIP_STM32F3 +source "arch/arm/src/stm32f3/Kconfig" +endif +if ARCH_CHIP_STM32F4 +source "arch/arm/src/stm32f4/Kconfig" +endif +if ARCH_CHIP_STM32G4 +source "arch/arm/src/stm32g4/Kconfig" +endif +if ARCH_CHIP_STM32L1 +source "arch/arm/src/stm32l1/Kconfig" +endif +if ARCH_CHIP_STM32F0 +source "arch/arm/src/stm32f0/Kconfig" +endif +if ARCH_CHIP_STM32L0 +source "arch/arm/src/stm32l0/Kconfig" +endif +if ARCH_CHIP_STM32G0 +source "arch/arm/src/stm32g0/Kconfig" +endif +if ARCH_CHIP_STM32C0 +source "arch/arm/src/stm32c0/Kconfig" endif if ARCH_CHIP_STM32F7 source "arch/arm/src/stm32f7/Kconfig" diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h deleted file mode 100644 index 1c62bcc3c4b..00000000000 --- a/arch/arm/include/stm32/chip.h +++ /dev/null @@ -1,2756 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* Check the STM32 family configuration. - * It must be done in arch/arm/src/stm32/Kconfig ! - */ - -#ifdef CONFIG_STM32_STM32F10XX -# define __HAVE_F1 1 -#else -# define __HAVE_F1 0 -#endif -#ifdef CONFIG_STM32_STM32F20XX -# define __HAVE_F2 1 -#else -# define __HAVE_F2 0 -#endif -#ifdef CONFIG_STM32_STM32F30XX -# define __HAVE_F30 1 -#else -# define __HAVE_F30 0 -#endif -#ifdef CONFIG_STM32_STM32F33XX -# define __HAVE_F33 1 -#else -# define __HAVE_F33 0 -#endif -#ifdef CONFIG_STM32_STM32F37XX -# define __HAVE_F37 1 -#else -# define __HAVE_F37 0 -#endif -#ifdef CONFIG_STM32_STM32F4XXX -# define __HAVE_F4 1 -#else -# define __HAVE_F4 0 -#endif -#ifdef CONFIG_STM32_STM32G4XXX -# define __HAVE_G4 1 -#else -# define __HAVE_G4 0 -#endif -#ifdef CONFIG_STM32_STM32L15XX -# define __HAVE_L1 1 -#else -# define __HAVE_L1 0 -#endif - -#if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \ - __HAVE_G4 + __HAVE_L1) != 1) -# error "Only one STM32 family must be selected !" -#endif - -#ifdef CONFIG_STM32_LOWDENSITY -# define __HAVE_LD 1 -#else -# define __HAVE_LD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMDENSITY -# define __HAVE_MD 1 -#else -# define __HAVE_MD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMPLUSDENSITY -# define __HAVE_MPD 1 -#else -# define __HAVE_MPD 0 -#endif -#ifdef CONFIG_STM32_HIGHDENSITY -# define __HAVE_HD 1 -#else -# define __HAVE_HD 0 -#endif - -#if (__HAVE_LD +__HAVE_MD + __HAVE_MPD + __HAVE_HD) > 1 -# error "Up to one density configuration must be selected" -#endif - -/* Get customizations for each supported chip and provide alternate function - * pin-mapping - * - * NOTE: Each GPIO pin may serve either for general purpose I/O or for a - * special alternate function (such as USART, CAN, USB, SDIO, etc.). That - * particular pin-mapping will depend on the package and STM32 family. If - * you are incorporating a new STM32 chip into NuttX, you will need to add - * the pin-mapping to a header file and to include that header file below. - * The chip-specific pin-mapping is defined in the chip datasheet. - */ - -/* STM32L EnergyLite Line ***************************************************/ - -/* STM32L151XX -- No LCD - * STM32L152XX -- With LCD - * - * STM32L15XCX -- 48-pins - * STM32L15XRX -- 64-pins - * STM32L15XVX -- 100-pins - * STM32L15XZX -- 144-pins - * - * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM - * - * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) - * - * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) - * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) - */ - -#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC , 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 21-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 109 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-G,H */ -# define STM32_NADC 1 /* ADC1, 40-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 12-channels */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-G,H */ - -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 Value Line ****************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ - || defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 High-density value Line ***************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100RE) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F102x8/102xB Medium Density USB Access Family **********************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Low Density Family ********************************************/ - -/* STM32F103C4 & STM32F103C6 */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 2 /* General timers TIM2,3 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timer */ -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Medium Density Performance Line *******************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 26 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 High Density Family *******************************************/ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-D */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* General timers TIM2-5 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 3 /* ADC1-3 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 112 /* GPIOA-G */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F105/F107 Connectivity Line ****************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2*/ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F205RG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207VC) || defined(CONFIG_ARCH_CHIP_STM32F207VE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207VF) || defined(CONFIG_ARCH_CHIP_STM32F207VG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 82 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207IC) || defined(CONFIG_ARCH_CHIP_STM32F207IE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207IF) || defined(CONFIG_ARCH_CHIP_STM32F207IG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 140 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207ZC) || defined(CONFIG_ARCH_CHIP_STM32F207ZE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207ZF) || defined(CONFIG_ARCH_CHIP_STM32F207ZG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -/* STM23 F3 Family **********************************************************/ - -/* Part Numbering: STM32Fssscfxxx - * - * Where - * sss = 302/303, 334 or 372/373 - * c = C (48pins) R (68 pins) V (100 pins) - * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) - * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) - * xxx = Package, temperature range, options (ignored here) - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 24 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 13 /* (13) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302C6) || defined(CONFIG_ARCH_CHIP_STM32F302C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302R6) || defined(CONFIG_ARCH_CHIP_STM32F302R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (2) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (2) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VD) || defined(CONFIG_ARCH_CHIP_STM32F303VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 84 /* GPIOA-F (depends on package) */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303ZD) || defined(CONFIG_ARCH_CHIP_STM32F303ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 115 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 2 /* (2) USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ -# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 - * (2) 32-bit general timers with DMA: TIM2 and TIM5 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ -# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -/* STM23 F4 Family **********************************************************/ - -/* STM32F01xB/C Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CB WLCSP49/UFQFPN48 128Kb No 10 - * STM32F401RB LQFP64 128Kb Yes 16 - * STM32F401VB UFBGA100/LQFP100 128Kb Yes 16 - * STM32F401CC WLCSP49/UFQFPN48 256Kb No 10 - * STM32F401RC LQFP64 256Kb Yes 16 - * STM32F401VC UFBGA100/LQFP100 256Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F01xD/E Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CD WLCSP49/UFQFPN48 384Kb No 10 - * STM32F401RD LQFP64 384Kb Yes 16 - * STM32F401VD UFBGA100/LQFP100 384Kb Yes 16 - * STM32F401CE WLCSP49/UFQFPN48 512Kb No 10 - * STM32F401RE LQFP64 512Kb Yes 16 - * STM32F401VE UFBGA100/LQFP100 512Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-4 */ -# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 81 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ -# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 113 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 168 /* GPIOA-K */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \ - defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NGPIO 114 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) -# define STM32_NGPIO 131 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NGPIO 161 /* GPIOA-K */ -# endif -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# endif -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431K) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 26 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 66 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431V) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-C, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 67 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-D, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 107 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474V) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#else -# error "Unsupported STM32 chip" -#endif - -/* Peripheral IP versions ***************************************************/ - -/* Peripheral IP versions are invariant and should be decided here, not in - * Kconfig. - * - * REVISIT: Currently only SPI IP version is handled here, with others being - * handled in Kconfig. Those others need to be gradually refactored - * and resolved here. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F20XX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32F30XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F33XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F37XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F4XXX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32G4XXX) -# define STM32_HAVE_IP_SPI_V4 - -#elif defined(CONFIG_STM32_STM32L15XX) -# define STM32_HAVE_IP_SPI_V1 - -#else -# error "Did not resolve peripheral IP versions!" -#endif - -/* NVIC priority levels *****************************************************/ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ - -#endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/arch/arm/include/stm32l1/chip.h b/arch/arm/include/stm32l1/chip.h new file mode 100644 index 00000000000..a8b532d3673 --- /dev/null +++ b/arch/arm/include/stm32l1/chip.h @@ -0,0 +1,491 @@ +/**************************************************************************** + * arch/arm/include/stm32l1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32L1_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32L1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +/* STM32L EnergyLite Line ***************************************************/ + +/* STM32L151XX -- No LCD + * STM32L152XX -- With LCD + * + * STM32L15XCX -- 48-pins + * STM32L15XRX -- 64-pins + * STM32L15XVX -- 100-pins + * STM32L15XZX -- 144-pins + * + * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM + * + * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) + * + * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) + * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) + */ + +#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC , 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 21-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 109 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-G,H */ +# define STM32_NADC 1 /* ADC1, 40-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 12-channels */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-G,H */ + +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F100 Value Line ****************************************************/ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V1 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32L1_CHIP_H */ diff --git a/arch/arm/include/stm32/stm32l15xxx_irq.h b/arch/arm/include/stm32l1/irq.h similarity index 90% rename from arch/arm/include/stm32/stm32l15xxx_irq.h rename to arch/arm/include/stm32l1/irq.h index 432d4b013c8..cba5263dd42 100644 --- a/arch/arm/include/stm32/stm32l15xxx_irq.h +++ b/arch/arm/include/stm32l1/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32l15xxx_irq.h + * arch/arm/include/stm32l1/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,12 +20,12 @@ * ****************************************************************************/ -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32L1_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L1_IRQ_H /**************************************************************************** * Included Files @@ -33,22 +33,45 @@ #include #include +#include /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) for low and medium density devices +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. */ -#if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY) +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32L1_LOWDENSITY) || defined(CONFIG_STM32L1_MEDIUMDENSITY) # define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ # define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ @@ -98,8 +121,6 @@ # define STM32_IRQ_NEXTINTS (45) -/* External interrupts (vectors >= 16) medium+ density devices */ - #elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY) # define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ @@ -160,9 +181,7 @@ # define STM32_IRQ_NEXTINTS (54) -/* External interrupts (vectors >= 16) high density devices */ - -#elif defined(CONFIG_STM32_HIGHDENSITY) +#elif defined(CONFIG_STM32L1_HIGHDENSITY) # define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ # define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ @@ -230,31 +249,4 @@ # define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32L1_IRQ_H */ diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index c235abddbee..34640d535af 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -227,9 +227,8 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() endif() - if(CONFIG_STM32_ADC - AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 - OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) + if(CONFIG_STM32_ADC AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) list(APPEND SRCS stm32_adc_m3m4_v1v2.c) endif() @@ -237,9 +236,8 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_sdadc_m3m4_v1.c) endif() - if(CONFIG_STM32_DAC - AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 - OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) + if(CONFIG_STM32_DAC AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) list(APPEND SRCS stm32_dac_m3m4_v1.c) endif() @@ -358,12 +356,7 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() if(CONFIG_ARCH_CORTEXM0) - list( - APPEND - SRCS - stm32_irq_m0_v1.c - stm32_start_m0_v1.c - stm32_lsi_m0_v1.c) + list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c) if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) list(APPEND SRCS stm32_gpio_m0_v1.c) diff --git a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c index e129ee671ce..f1c195a43cd 100644 --- a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c @@ -1093,7 +1093,7 @@ int stm32_dma2dinitialize(void) stm32_dma2duninitialize(); /* Enable dma2d is done in rcc_enableahb1, see - * arch/arm/src/stm32/stm32f40xxx_rcc.c + * arch/arm/src/stm32f4/stm32_rcc.c */ #ifdef CONFIG_STM32_FB_CMAP diff --git a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c index 6fb57a23624..756c7031663 100644 --- a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -20,7 +20,7 @@ * ****************************************************************************/ -/* Ported from arch/arm/src/stm32/stm32_dma_v1mux.c */ +/* Ported from arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c */ /**************************************************************************** * Included Files diff --git a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c index c9695564c93..8c72dd6b209 100644 --- a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c @@ -47,7 +47,7 @@ #include "stm32_gpio.h" #include "stm32_rcc.h" -/* Ported from arch/arm/src/stm32/stm32_fdcan.c */ +/* Ported from arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c */ /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt deleted file mode 100644 index f36e41d25df..00000000000 --- a/arch/arm/src/stm32/CMakeLists.txt +++ /dev/null @@ -1,57 +0,0 @@ -# ############################################################################## -# arch/arm/src/stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -list( - APPEND - SRCS - stm32_allocateheap.c - stm32_start.c - stm32_rcc.c - stm32_lse.c - stm32_lsi.c - stm32_irq.c - stm32_lowputc.c) - -if(CONFIG_STM32_TICKLESS_TIMER) - list(APPEND SRCS stm32_tickless.c) -else() - list(APPEND SRCS stm32_timerisr.c) -endif() - -if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) -endif() - -if(NOT CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -list(APPEND SRCS stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c) - -if(NOT CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pminitialize.c) -endif() - -target_sources(arch PRIVATE ${SRCS}) -add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig deleted file mode 100644 index 82d831fa087..00000000000 --- a/arch/arm/src/stm32/Kconfig +++ /dev/null @@ -1,2675 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32 Configuration Options" - -config STM32_COMMON_PERIPHERALS - bool - default y - depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - select STM32_HAVE_COMP if STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX - select STM32_HAVE_DCMI if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_DMA2 if !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) - select STM32_HAVE_DMA2D if STM32_STM32F429 - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_HASH if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_I2C1 - select STM32_HAVE_LCD if STM32_STM32L15XX - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG if STM32_STM32L15XX || STM32_STM32F30XX - select STM32_HAVE_SYSCFG if STM32_STM32F33XX || STM32_STM32F37XX - select STM32_HAVE_SYSCFG if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_SYSCFG if STM32_STM32G4XXX || STM32_CONNECTIVITYLINE - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - -choice - prompt "STM32 Chip Selection" - default ARCH_CHIP_STM32F103ZE - depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - -config ARCH_CHIP_STM32L151C6 - bool "STM32L151C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151C8 - bool "STM32L151C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151CB - bool "STM32L151CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R6 - bool "STM32L151R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R8 - bool "STM32L151R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151RB - bool "STM32L151RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V6 - bool "STM32L151V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V8 - bool "STM32L151V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151VB - bool "STM32L151VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L152C6 - bool "STM32L152C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152C8 - bool "STM32L152C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152CB - bool "STM32L152CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152R6 - bool "STM32L152R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152R8 - bool "STM32L152R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152RB - bool "STM32L152RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152V6 - bool "STM32L152V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152V8 - bool "STM32L152V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152VB - bool "STM32L152VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152CC - bool "STM32L152CC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152RC - bool "STM32L152RC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152VC - bool "STM32L152VC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L151RE - bool "STM32L151RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152RE - bool "STM32L152RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151VE - bool "STM32L151VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152VE - bool "STM32L152VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151QE - bool "STM32L151QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152QE - bool "STM32L152QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151ZE - bool "STM32L151ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152ZE - bool "STM32L152ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L162ZD - bool "STM32L162ZD" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L162VE - bool "STM32L162VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32F100C8 - bool "STM32F100C8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100CB - bool "STM32F100CB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100R8 - bool "STM32F100R8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RB - bool "STM32F100RB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RC - bool "STM32F100RC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RD - bool "STM32F100RD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RE - bool "STM32F100RE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100V8 - bool "STM32F100V8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VB - bool "STM32F100VB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VC - bool "STM32F100VC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VD - bool "STM32F100VD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VE - bool "STM32F100VE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F102CB - bool "STM32F102CB" - select STM32_STM32F10XX - select STM32_USBACCESSLINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103T8 - bool "STM32F103T8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103TB - bool "STM32F103TB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103C4 - bool "STM32F103C4" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_LOWDENSITY - -config ARCH_CHIP_STM32F103C8 - bool "STM32F103C8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103CB - bool "STM32F103CB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103R8 - bool "STM32F103R8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RB - bool "STM32F103RB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RC - bool "STM32F103RC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RD - bool "STM32F103RD" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RE - bool "STM32F103RE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RG - bool "STM32F103RG" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103V8 - bool "STM32F103V8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VB - bool "STM32F103VB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VC - bool "STM32F103VC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VE - bool "STM32F103VE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103ZE - bool "STM32F103ZE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105VB - bool "STM32F105VBT7" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105RB - bool "STM32F105RB" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F107VC - bool "STM32F107VC" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F205RG - bool "STM32F205RG" - select STM32_STM32F20XX - select STM32_STM32F205 - -config ARCH_CHIP_STM32F207VC - bool "STM32F207VC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VE - bool "STM32F207VE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VF - bool "STM32F207VF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VG - bool "STM32F207VG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IC - bool "STM32F207IC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IE - bool "STM32F207IE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IF - bool "STM32F207IF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IG - bool "STM32F207IG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZC - bool "STM32F207ZC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZE - bool "STM32F207ZE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZF - bool "STM32F207ZF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZG - bool "STM32F207ZG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F302K6 - bool "STM32F302K6" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302K8 - bool "STM32F302K8" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302C6 - bool "STM32F302C6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302C8 - bool "STM32F302C8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R6 - bool "STM32F302R6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R8 - bool "STM32F302R8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302CB - bool "STM32F302CB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302CC - bool "STM32F302CC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302RB - bool "STM32F302RB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302RC - bool "STM32F302RC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VB - bool "STM32F302VB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VC - bool "STM32F302VC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F303K6 - bool "STM32F303K6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303K8 - bool "STM32F303K8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303C6 - bool "STM32F303C6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303C8 - bool "STM32F303C8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303CB - bool "STM32F303CB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303CC - bool "STM32F303CC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RB - bool "STM32F303RB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RC - bool "STM32F303RC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RD - bool "STM32F303RD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RE - bool "STM32F303RE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VB - bool "STM32F303VB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VC - bool "STM32F303VC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VD - bool "STM32F303VD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303VE - bool "STM32F303VE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZD - bool "STM32F303ZD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZE - bool "STM32F303ZE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F334K4 - bool "STM32F334K4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K6 - bool "STM32F334K6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K8 - bool "STM32F334K8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C4 - bool "STM32F334C4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C6 - bool "STM32F334C6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C8 - bool "STM32F334C8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R4 - bool "STM32F334R4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R6 - bool "STM32F334R6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R8 - bool "STM32F334R8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F372C8 - bool "STM32F372C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372R8 - bool "STM32F372R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372V8 - bool "STM32F372V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CB - bool "STM32F372CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RB - bool "STM32F372RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VB - bool "STM32F372VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CC - bool "STM32F372CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RC - bool "STM32F372RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VC - bool "STM32F372VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373C8 - bool "STM32F373C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373R8 - bool "STM32F373R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373V8 - bool "STM32F373V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CB - bool "STM32F373CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RB - bool "STM32F373RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VB - bool "STM32F373VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CC - bool "STM32F373CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RC - bool "STM32F373RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VC - bool "STM32F373VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F401CB - bool "STM32F401CB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RB - bool "STM32F401RB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VB - bool "STM32F401VB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CC - bool "STM32F401CC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RC - bool "STM32F401RC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VC - bool "STM32F401VC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CD - bool "STM32F401CD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RD - bool "STM32F401RD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VD - bool "STM32F401VD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401CE - bool "STM32F401CE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RE - bool "STM32F401RE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VE - bool "STM32F401VE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F410RB - bool "STM32F410RB" - select STM32_STM32F4XXX - select STM32_STM32F410 - -config ARCH_CHIP_STM32F411CE - bool "STM32F411CE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411RE - bool "STM32F411RE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411VE - bool "STM32F411VE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F412CE - bool "STM32F412CE" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F412ZG - bool "STM32F412ZG" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F405RG - bool "STM32F405RG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405VG - bool "STM32F405VG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405ZG - bool "STM32F405ZG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F407VE - bool "STM32F407VE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407VG - bool "STM32F407VG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZE - bool "STM32F407ZE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZG - bool "STM32F407ZG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IE - bool "STM32F407IE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IG - bool "STM32F407IG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F427V - bool "STM32F427V" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427Z - bool "STM32F427Z" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427I - bool "STM32F427I" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F429V - bool "STM32F429V" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429Z - bool "STM32F429Z" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429I - bool "STM32F429I" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429B - bool "STM32F429B" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429N - bool "STM32F429N" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F446M - bool "STM32F446M" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446R - bool "STM32F446R" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446V - bool "STM32F446V" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446Z - bool "STM32F446Z" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F469A - bool "STM32F469A" - select STM32_STM32F4XXX - select STM32_STM32F469 - -config ARCH_CHIP_STM32F469I - bool "STM32F469I" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469B - bool "STM32F469B" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469N - bool "STM32F469N" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32G431K - bool "STM32G431K" - select STM32_STM32G43XX - select STM32_STM32G4XXK - select STM32_STM32G431K - -config ARCH_CHIP_STM32G431C - bool "STM32G431C" - select STM32_STM32G43XX - select STM32_STM32G4XXC - select STM32_STM32G431C - -config ARCH_CHIP_STM32G431R - bool "STM32G431R" - select STM32_STM32G43XX - select STM32_STM32G4XXR - select STM32_STM32G431R - -config ARCH_CHIP_STM32G431M - bool "STM32G431M" - select STM32_STM32G43XX - select STM32_STM32G4XXM - select STM32_STM32G431M - -config ARCH_CHIP_STM32G431V - bool "STM32G431V" - select STM32_STM32G43XX - select STM32_STM32G4XXV - select STM32_STM32G431V - -config ARCH_CHIP_STM32G474C - bool "STM32G474C" - select STM32_STM32G47XX - select STM32_STM32G4XXC - select STM32_STM32G474C - -config ARCH_CHIP_STM32G474M - bool "STM32G474M" - select STM32_STM32G47XX - select STM32_STM32G4XXM - select STM32_STM32G474M - -config ARCH_CHIP_STM32G474R - bool "STM32G474R" - select STM32_STM32G47XX - select STM32_STM32G4XXR - select STM32_STM32G474R - select STM32_HAVE_USBFS - -config ARCH_CHIP_STM32G474Q - bool "STM32G474Q" - select STM32_STM32G47XX - select STM32_STM32G4XXQ - select STM32_STM32G474Q - -config ARCH_CHIP_STM32G474V - bool "STM32G474V" - select STM32_STM32G47XX - select STM32_STM32G4XXV - select STM32_STM32G474V - -endchoice - -config STM32_FLASH_CONFIG_DEFAULT - bool - -config STM32_FLASH_CONFIG_Z - bool - -config STM32_STM32L15XX - select STM32_HAVE_DMA1 - select STM32_HAVE_COMP - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_LCD - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_L1 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V1 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM3 - select STM32_ENERGYLITE - select STM32_HAVE_USBDEV - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_STM32F10XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 if !STM32F1_VALUELINE || STM32F1_HIGHDENSITY - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG if STM32F1_CONNECTIVITYLINE - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_BKP - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE - select STM32_HAVE_IP_SPI_V1 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_USART_V1 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM3 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_RTC_COUNTER - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_IP_DBGMCU_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1_BASIC - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_CONNECTIVITYLINE - bool - default n - select STM32_HAVE_OTGFS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - -config STM32_PERFORMANCELINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - -config STM32_USBACCESSLINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_SPI2 - -config STM32_MEDIUMPLUSDENSITY - bool - default n - -config STM32_HIGHDENSITY - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_MEDIUMDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_LOWDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 if !STM32_VALUELINE - -config STM32_STM32F20XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_DCMI - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_HASH - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V2_STREAM - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F2F4 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_OTGHS_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_BKPSRAM - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V2 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM3 - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_OTGFS - select STM32_HAVE_OTGHS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_STM32F205 - bool - default n - -config STM32_STM32F207 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_ETHMAC - -config STM32_STM32F30XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_IP_USART_V3 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V2 - select STM32_HAVE_IP_ADC_M3M4_V2 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - -config STM32_STM32F302 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_USBDEV - -config STM32_STM32F303 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_CCM - select STM32_HAVE_TIM7 - -config STM32_STM32F33XX - select STM32_HAVE_DMA1 - select STM32_HAVE_COMP - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_PWR - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_IP_USART_V3 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_HRTIM1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP6 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_CCM - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V2 - select STM32_HAVE_IP_ADC_M3M4_V2 - select STM32_HAVE_IP_COMP_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - -config STM32_STM32F37XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_IP_SDADC_M3M4_V1 - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_USART_V3 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_USBDEV - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1_BASIC - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - -config STM32_STM32F4XXX - select STM32_HAVE_OTGHS - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_DCMI - select STM32_HAVE_HASH - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V2_STREAM - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F2F4 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OTGHS_M3M4_V1 - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_F4 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_BKPSRAM - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V2 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_LTDC_M3M4_V1 if STM32_HAVE_LTDC - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select ARCH_CORTEXM4 - select STM32_HAVE_PWR - select ARCH_HAVE_FPU - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_STM32F401xBC - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401xDE - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401 - bool - default n - select ARCH_CORTEXM4 - select STM32_STM32F4XXX - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F410 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI5 - select STM32_HAVE_DAC1 - -config STM32_STM32F411 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F412 - bool - default n - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_USART3 - select STM32_HAVE_USART2 - select STM32_HAVE_USART6 - select STM32_HAVE_I2C1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI1 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_OTGFS - select STM32_HAVE_I2SPLL - -config STM32_STM32F405 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_OTGFS - -config STM32_STM32F407 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_OTGFS - -# This is really 427/437, but we treat the two the same. - -config STM32_STM32F427 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SPI6 - select STM32_HAVE_I2SPLL - -# This is really 429/439, but we treat the two the same. - -config STM32_STM32F429 - select STM32_HAVE_DMA2D - select STM32_HAVE_IP_DMA2D_M3M4_V1 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F446 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - -# This is really 469/479, but we treat the two the same. - -config STM32_STM32F469 - select STM32_HAVE_DMA2D - select STM32_HAVE_IP_DMA2D_M3M4_V1 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - -config STM32_STM32G4XXX - select STM32_HAVE_DMA1 - select STM32_HAVE_COMP - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_CORDIC_M3M4_V1 if STM32_HAVE_CORDIC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH_DMAMUX - select STM32_HAVE_IP_EXTI_V2 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_G4 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_PWR - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V4 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_DBGMCU_M3M4_V3 - select STM32_HAVE_IP_ADC_M3M4_V2 - select STM32_HAVE_IP_COMP_M3M4_V2 - select STM32_HAVE_IP_DAC_M3M4_V2 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V3 - -config STM32_STM32G4_CAT2 - bool - default n - -config STM32_STM32G4_CAT3 - bool - default n - -config STM32_STM32G4_CAT4 - bool - default n - -config STM32_STM32G4XXK - bool - default n - -config STM32_STM32G4XXC - bool - default n - -config STM32_STM32G4XXR - bool - default n - -config STM32_STM32G4XXM - bool - default n - -config STM32_STM32G4XXV - bool - default n - -config STM32_STM32G4XXP - bool - default n - -config STM32_STM32G4XXQ - bool - default n - -config STM32_STM32G43XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT2 - select STM32_HAVE_ADC2 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC3 - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G431K - bool - default n - -config STM32_STM32G431C - bool - default n - select STM32_HAVE_USART3 - -config STM32_STM32G431R - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431M - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431V - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G47XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT3 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_ADC5 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP5 - select STM32_HAVE_COMP6 - select STM32_HAVE_COMP7 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_DAC3 - select STM32_HAVE_DAC4 - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_FSMC - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_HRTIM1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_I2C4 - select STM32_HAVE_I2S3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_OPAMP4 - select STM32_HAVE_OPAMP5 - select STM32_HAVE_OPAMP6 - select STM32_HAVE_QSPI - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM20 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G474C - bool - default n - select STM32_HAVE_FDCAN3 - -config STM32_STM32G474M - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474R - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474Q - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474V - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -# --- restored family-specific symbols over-deleted by move-to-common (split recreates per-family) --- -if ARCH_CHIP_STM32 - -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY - -choice - prompt "CAN1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_CAN1 - default STM32_CAN1_NO_REMAP - -config STM32_CAN1_NO_REMAP - bool "No pin remapping" - -config STM32_CAN1_REMAP1 - bool "CAN1 alternate pin remapping #1" - -config STM32_CAN1_REMAP2 - bool "CAN1 alternate pin remapping #2" - -endchoice - -config STM32_CAN2_REMAP - bool "CAN2 Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_CAN2 - -config STM32_CEC_REMAP - bool "CEC Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_CEC - -config STM32_ETH_REMAP - bool "Ethernet Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC - -config STM32_I2C1_REMAP - bool "I2C1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2C1 - -config STM32_SPI1_REMAP - bool "SPI1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI1 - -config STM32_SPI3_REMAP - bool "SPI3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE - -config STM32_I2S3_REMAP - bool "I2S3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2S3 && !STM32_VALUELINE - -choice - prompt "TIM1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM1 - default STM32_TIM1_NO_REMAP - -config STM32_TIM1_NO_REMAP - bool "No pin remapping" - -config STM32_TIM1_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM1_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -choice - prompt "TIM2 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM2 - default STM32_TIM2_NO_REMAP - -config STM32_TIM2_NO_REMAP - bool "No pin remapping" - -config STM32_TIM2_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM2_PARTIAL_REMAP_1 - bool "Partial pin remapping #1" - -config STM32_TIM2_PARTIAL_REMAP_2 - bool "Partial pin remapping #2" - -endchoice - -choice - prompt "TIM3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM3 - default STM32_TIM3_NO_REMAP - -config STM32_TIM3_NO_REMAP - bool "No pin remapping" - -config STM32_TIM3_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -config STM32_TIM4_REMAP - bool "TIM4 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM4 - -config STM32_TIM9_REMAP - bool "TIM9 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM9 - -config STM32_TIM10_REMAP - bool "TIM10 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM10 - -config STM32_TIM11_REMAP - bool "TIM11 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM11 - -config STM32_TIM12_REMAP - bool "TIM12 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM12 - -config STM32_TIM13_REMAP - bool "TIM13 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM13 - -config STM32_TIM14_REMAP - bool "TIM14 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM14 - -config STM32_TIM15_REMAP - bool "TIM15 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM15 - -config STM32_TIM16_REMAP - bool "TIM16 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM16 - -config STM32_TIM17_REMAP - bool "TIM17 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM17 - -config STM32_USART1_REMAP - bool "USART1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART1 - -config STM32_USART2_REMAP - bool "USART2 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART2 - -choice - prompt "USART3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_USART3 - default STM32_USART3_NO_REMAP - -config STM32_USART3_NO_REMAP - bool "No pin remapping" - -config STM32_USART3_FULL_REMAP - bool "Full pin remapping" - -config STM32_USART3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -endif diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h deleted file mode 100644 index b499a2cc557..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h +++ /dev/null @@ -1,206 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h deleted file mode 100644 index ee01472c30a..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h deleted file mode 100644 index 18fc6f1b8b9..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h +++ /dev/null @@ -1,341 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ - -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: Word length */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ -#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ -#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ - USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE) - -/* Control register 2 */ - -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ -# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ -# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ -# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ -#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */ -#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ -#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ -#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */ -#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDRMAT (0 << USART_CR3_WUS_SHIFT) /* Active on address match */ -# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */ -# define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */ - -#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ - -/* Baud Rate Register */ - -#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ -#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) -#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */ -#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT) -#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/ -#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) - -/* Request register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt & status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ -#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ -#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ - -#define USART_ISR_ALLBITS (0x007fdfff) - -/* Interrupt flag clear register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ - -#define USART_ICR_ALLBITS (0x00121b5f) - -/* Receive data register */ - -#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */ -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) - -/* Transmit data register */ - -#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F1/F2/F4 Status register */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h deleted file mode 100644 index edfb2a0cc71..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h +++ /dev/null @@ -1,236 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 6 -# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 7 -# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h deleted file mode 100644 index 98990ba21e3..00000000000 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h +++ /dev/null @@ -1,439 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* BAUD Rate Register */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt Flag Clear Register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ - -/* Register Addresses *******************************************************/ -#if (STM32_NLPUART > 0) -# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_LPUART1_BRR (STM32_LPUART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_LPUART1_RQR (STM32_LPUART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_LPUART1_ISR (STM32_LPUART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_LPUART1_ICR (STM32_LPUART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_LPUART1_RDR (STM32_LPUART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_LPUART1_TDR (STM32_LPUART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 0) -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 1) -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 2) -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 3) -# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 4) -# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control Register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0 - USART Enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1 - USART Enable in low power Mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2 - Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3 - Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4 - IDLE Interrupt Enable */ -#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5 in FIFO mode - Rx FIFO Not Empty Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5 in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6 - Transmission Complete Interrupt Enable */ -#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7 in FIFO mode - Tx FIFO Not Full Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7 in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8 - PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9 - Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10 - Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11 - Receiver Wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12 - Word length - Bit 0 */ -#define USART_CR1_MME (1 << 13) /* Bit 13 - Mute Mode Enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14 - Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15 - Oversampling by 8-bit or 16-bit mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) -# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) -# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26 - Receive Time Out interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27 - End of Block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 28 - Word length - Bit 1 */ -#define USART_CR1_FIFOEN (1 << 29) /* Bit 29 - FIFO mode enable */ -#define USART_CR1_TXFEIE (1 << 30) /* Bit 30 - TXFIFO empty interrupt enable */ -#define USART_CR1_RXFFIE (1 << 31) /* Bit 31 - RXFIFO Full interrupt enable */ - -#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1) - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | \ - USART_CR1_EOBIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -#define LPUART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \ - USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -/* Control Register 2 */ - -#define USART_CR2_SLVEN (1 << 0) /* Synchronous Slave Mode Enable */ -#define USART_CR2_DIS_NSS (1 << 3) /* Slave Select (NSS) Pin Ignore For SPI */ -#define USART_CR2_ADDM7 (1 << 4) /* 7-Bit / 4-Bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Stop Bit Mode */ -#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 1 Stop Bit */ -# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 0.5 Stop Bit */ -# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 2 Stop Bits */ -# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 1.5 Stop Bits */ -#define USART_CR2_LINEN (1 << 14) /* LIN Mode Enable */ -#define USART_CR2_SWAP (1 << 15) /* Swap TX/RX Pins */ -#define USART_CR2_RXINV (1 << 16) /* RX Pin Active Level Inversion */ -#define USART_CR2_TXINV (1 << 17) /* TX Pin Active Level Inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Binary Data Inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* MSB First */ -#define USART_CR2_ABREN (1 << 20) /* Auto BAUD-Rate Enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Auto BAUD-Rate Detection Mode */ -#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* Measurement of Start Bit */ -# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* Falling Edge To Falling Edge */ -# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 0X7F Frame Detection */ -# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 0X55 Frame Detection */ -#define USART_CR2_RTOEN (1 << 23) /* Receiver Time-Out Enable */ -#define USART_CR2_ADD8_SHIFT (24) /* Address of the USART Node */ -#define USART_CR2_ADD8_MASK (0xff << USART_CR2_ADD8_SHIFT) - -/* Control Register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* IrDA Mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* SmartCard NACK Enable */ -#define USART_CR3_SCEN (1 << 5) /* SmartCard Mode Enable */ -#define USART_CR3_DMAR (1 << 6) /* DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* One Sample Bit Method Enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Driver Enable Mode */ -#define USART_CR3_DEP (1 << 15) -#define USART_CR3_SCARCNT_SHIFT (17) /* SmartCard Auto-Retry Count */ -#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT) -# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK) -#define USART_CR3_WUS_SHIFT (20) /* Wake Up From Low Power Mode Interrupt Flag Selection) */ -#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* On Address Match */ -# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* On Start Bit Detection */ -# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* On RXNE/RXFNE */ -#define USART_CR3_WUFIE (1 << 22) /* Wake Up From Low Power Mode Interrupt Enable */ -#define USART_CR3_TXFTIE (1 << 23) /* Transmit FIFO Threshold Interrupt Enable */ -#define USART_CR3_TCBGTIE (1 << 24) /* Transmit Complete Before Guard Time Interrupt Enable */ -#define USART_CR3_RXFTCFG_SHIFT (25) /* Receive FIFO Threshold Configuration */ -#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/2 Depth */ -# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Is Full */ -#define USART_CR3_RXFTIE (1 << 28) /* Receive FIFO Threshold Interrupt Enable */ -#define USART_CR3_TXFTCFG_SHIFT (29) /* Transmit FIFO Threshold Configuration */ -#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/2 Depth */ -# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Is Full */ - -/* BAUD Rate Register */ - -/* Full BRR field */ - -#define USART_BRR_SHIFT (0) -#define USART_BRR_MASK (0xffff << USART_BRR_BRR_SHIFT) -# define USART_BRR(n) (((n) << USART_BRR_BRR_SHIFT) & USART_BRR_BRR_MASK) - -/* Partial BRR field BRR[3:0]: - * - * When OVER8 = 0: BRR[3:0] = USARTDIV[3:0] - * - * When OVER8 = 1: BRR[2:0] = (USARTDIV[3:0] >> 1) and - * BRR[3] must be kept cleared. - */ - -#define USART_BRR_0_3_SHIFT (0) -#define USART_BRR_0_3_MASK (0xf << USART_BRR_0_3_SHIFT) -# define USART_BRR_0_3(n) (((n) << USART_BRR_0_3_SHIFT) & USART_BRR_0_3_MASK) - -/* Partial BRR field BRR[15:4]: - * BRR[15:4] = USARTDIV[15:4] - */ - -#define USART_BRR_4_15_SHIFT (4) -#define USART_BRR_4_15_MASK (0xfff << USART_BRR_4_15_SHIFT) -# define USART_BRR_4_15(n) (((n) << USART_BRR_4_15_SHIFT) & USART_BRR_4_15_MASK) - -/* Guard Time and Prescaler Register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Prescaler Value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK) -#define USART_GTPR_GT_SHIFT (8) /* Guard Time Value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) -# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK) - -/* Receiver Timeout Register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Receiver Time Out Value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK) -#define USART_RTOR_BLEN_SHIFT (24) /* Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) -# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK) - -/* Request Register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */ - -/* Interrupt and Status Register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */ -#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */ -#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */ -#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */ -#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */ -#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */ -#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto BAUD Rate Error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto BAUD Rate Flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */ -#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */ -#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */ -#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */ -#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */ -#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */ -#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Flag */ - -#define USART_ISR_ALLBITS (0x0fffffff) - -/* Interrupt Flag Clear Register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */ -#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */ -#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */ -#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */ - -/* Receive Data Register */ - -#define USART_RDR_SHIFT (0) -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) -# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK) - -/* Transmit Data Register */ - -#define USART_TDR_SHIFT (0) -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK) - -/* Prescaler Register */ - -#define USART_PRESC_PRESCALER_SHIFT (0) -#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* Compatibility with F1/F2/F4 Status Register names */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -#define USART_CR1_M USART_CR1_M0 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h b/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h deleted file mode 100644 index f3cb64060db..00000000000 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h +++ /dev/null @@ -1,208 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0x1ff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* L15 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H */ diff --git a/arch/arm/src/stm32/stm32_pm.h b/arch/arm/src/stm32/stm32_pm.h deleted file mode 100644 index 7d66d3b209f..00000000000 --- a/arch/arm/src/stm32/stm32_pm.h +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pm.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_PM_H -#define __ARCH_ARM_SRC_STM32_STM32_PM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmstop - * - * Description: - * Enter STOP mode. - * - * Input Parameters: - * lpds - true: To further reduce power consumption in Stop mode, put the - * internal voltage regulator in low-power mode using the LPDS bit - * of the Power control register (PWR_CR). - * - * Returned Value: - * Zero means that the STOP was successfully entered and the system has - * been re-awakened. The internal voltage regulator is back to its - * original state. Otherwise, STOP mode did not occur and a negated - * errno value is returned to indicate the cause of the failure. - * - ****************************************************************************/ - -int stm32_pmstop(bool lpds); - -/**************************************************************************** - * Name: stm32_pmstandby - * - * Description: - * Enter STANDBY mode. - * - * Input Parameters: - * None - * - * Returned Value: - * On success, this function will not return (STANDBY mode can only be - * terminated with a reset event). Otherwise, STANDBY mode did not occur - * and a negated errno value is returned to indicate the cause of the - * failure. - * - ****************************************************************************/ - -int stm32_pmstandby(void); - -/**************************************************************************** - * Name: stm32_pmsleep - * - * Description: - * Enter SLEEP mode. - * - * Input Parameters: - * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is - * executed, the MCU enters Sleep mode as soon as it - * exits the lowest priority ISR. - * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep - * mode as soon as WFI or WFE instruction is executed. - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pmsleep(bool sleeponexit); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_PM_H */ diff --git a/arch/arm/src/stm32/stm32_rcc.h b/arch/arm/src/stm32/stm32_rcc.h deleted file mode 100644 index cfead6ee3e4..00000000000 --- a/arch/arm/src/stm32/stm32_rcc.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_rcc.h" -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mco1config - * - * Description: - * Selects the clock source to output on MCO1 pin (PA8). PA8 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO1 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1_HSI, RCC_CFGR_MCO1_LSE, - * RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1_PLL} - * div - One of the definitions for the RCC_CFGR_MCO1PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1PRE_NONE, RCC_CFGR_MCO1PRE_DIV2, - * RCC_CFGR_MCO1PRE_DIV3, RCC_CFGR_MCO1PRE_DIV4, RCC_CFGR_MCO1PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco1config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcoconfig - * - * Description: - * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. - * PA8 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO definitions from - * chip/stm32f10xxx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, - * RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, - * RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) -static inline void stm32_mcoconfig(uint32_t source) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO_MASK); - regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcodivconfig - * - * Description: - * Selects the clock source to output and clock divider on MC pin (PA4) for - * stm32l1xxx. PA4 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCOSEL definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOSEL_DISABLED, RCC_CFGR_MCOSEL_SYSCLK, - * RCC_CFGR_MCOSEL_HSICLK, RCC_CFGR_MCOSEL_MSICLK, - * RCC_CFGR_MCOSEL_HSECLK, RCC_CFGR_MCOSEL_PLLCLK, - * RCC_CFGR_MCOSEL_LSICLK, RCC_CFGR_MCOSEL_LSECLK} - * divider - One of the definitions for the RCC_CFGR_MCOPRE definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOPRE_DIV1, RCC_CFGR_MCOPRE_DIV2, - * RCC_CFGR_MCOPRE_DIV4, RCC_CFGR_MCOPRE_DIV8, RCC_CFGR_MCOPRE_DIV16} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCOSEL_MASK); - regval |= (source & RCC_CFGR_MCOSEL_MASK); - regval &= ~(RCC_CFGR_MCOPRE_MASK); - regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mco2config - * - * Description: - * Selects the clock source to output on MCO2 pin (PC9). PC9 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO2 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2_SYSCLK, RCC_CFGR_MCO2_PLLI2S, - * RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2_PLL} - * div - One of the definitions for the RCC_CFGR_MCO2PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2PRE_NONE, RCC_CFGR_MCO2PRE_DIV2, - * RCC_CFGR_MCO2PRE_DIV3, RCC_CFGR_MCO2PRE_DIV4, RCC_CFGR_MCO2PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco2config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to establish the clock settings based on the values in board.h. - * This function (by default) will reset most everything, enable the PLL, - * and enable peripheral clocking for all periperipherals enabled in the - * NuttX configuration file. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_clockconfig(void); - -/**************************************************************************** - * Name: stm32_board_clockconfig - * - * Description: - * Any STM32 board may replace the "standard" board clock configuration - * logic with its own, custom clock configuration logic. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32_board_clockconfig(void); -#endif - -/**************************************************************************** - * Name: stm32_clockenable - * - * Description: - * Re-enable the clock and restore the clock settings based on settings in - * board.h. - * This function is only available to support low-power modes of operation: - * When re-awakening from deep-sleep modes, it is necessary to re-enable/ - * re-start the PLL - * - * This functional performs a subset of the operations performed by - * stm32_clockconfig(): It does not reset any devices, and it does not - * reset the currently enabled peripheral clocks. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_clockenable(void); -#endif - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) Oscillator. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void); - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.h b/arch/arm/src/stm32/stm32_userspace.h deleted file mode 100644 index 8cdb47e52ff..00000000000 --- a/arch/arm/src/stm32/stm32_userspace.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H -#define __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_userspace - * - * Description: - * For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_PROTECTED -void stm32_userspace(void); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index 14f9ccda020..327dc5c59a7 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -49,7 +49,7 @@ #include "stm32_rcc.h" #include "stm32_can.h" -/* Ported form arch/arm/src/stm32/stm32_can_sock.c */ +/* Ported form arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c */ /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index 5932b37c80d..9f51388aaee 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -78,7 +78,8 @@ * * Currently, up to two FOC instances are supported. * - * This implementation is based on arch/arm/src/stm32/stm32_foc.c + * This implementation is based on + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c */ /* Verify system configuration **********************************************/ diff --git a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt b/arch/arm/src/stm32l1/CMakeLists.txt similarity index 84% rename from boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt rename to arch/arm/src/stm32l1/CMakeLists.txt index 1f40202c329..1067ff19101 100644 --- a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt +++ b/arch/arm/src/stm32l1/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt +# arch/arm/src/stm32l1/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -20,4 +20,9 @@ # # ############################################################################## -add_subdirectory(src) +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig new file mode 100644 index 00000000000..129f60d8271 --- /dev/null +++ b/arch/arm/src/stm32l1/Kconfig @@ -0,0 +1,356 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 L1 configuration" + +if ARCH_CHIP_STM32L1 + +choice + prompt "STM32L1 Chip Selection" + depends on ARCH_CHIP_STM32L1 + +config ARCH_CHIP_STM32L151C6 + bool "STM32L151C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151C8 + bool "STM32L151C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151CB + bool "STM32L151CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R6 + bool "STM32L151R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R8 + bool "STM32L151R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151RB + bool "STM32L151RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V6 + bool "STM32L151V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V8 + bool "STM32L151V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151VB + bool "STM32L151VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L152C6 + bool "STM32L152C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152C8 + bool "STM32L152C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152CB + bool "STM32L152CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152R6 + bool "STM32L152R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152R8 + bool "STM32L152R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152RB + bool "STM32L152RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152V6 + bool "STM32L152V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152V8 + bool "STM32L152V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152VB + bool "STM32L152VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152CC + bool "STM32L152CC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152RC + bool "STM32L152RC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152VC + bool "STM32L152VC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L151RE + bool "STM32L151RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152RE + bool "STM32L152RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151VE + bool "STM32L151VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152VE + bool "STM32L152VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151QE + bool "STM32L151QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152QE + bool "STM32L152QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151ZE + bool "STM32L151ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152ZE + bool "STM32L152ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L162ZD + bool "STM32L162ZD" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L162VE + bool "STM32L162VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with + 4x44/8x40 LCD interface + +endchoice + +endif + +config STM32_STM32L15XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM3 + select STM32_ENERGYLITE + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_RTC_SUBSECONDS if !STM32L1_LOWDENSITY + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_L1 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32L1_MEDIUMPLUSDENSITY + bool + default n + +config STM32L1_HIGHDENSITY + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_MEDIUMDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_LOWDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32l1/Make.defs similarity index 64% rename from arch/arm/src/stm32/Make.defs rename to arch/arm/src/stm32l1/Make.defs index a7cf6decf4b..f0e835622db 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32l1/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/stm32/Make.defs +# arch/arm/src/stm32l1/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -22,27 +22,6 @@ include armv7-m/Make.defs -CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c -CHIP_CSRCS += stm32_lsi.c stm32_irq.c stm32_lowputc.c - -ifdef CONFIG_STM32_TICKLESS_TIMER -CHIP_CSRCS += stm32_tickless.c -else -CHIP_CSRCS += stm32_timerisr.c -endif - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c -endif - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32_idle.c -endif - -CHIP_CSRCS += stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c - -ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CHIP_CSRCS += stm32_pminitialize.c -endif +CHIP_CSRCS = stm32_rcc.c include common/stm32/Make.defs diff --git a/arch/arm/src/stm32/stm32_start.h b/arch/arm/src/stm32l1/chip.h similarity index 64% rename from arch/arm/src/stm32/stm32_start.h rename to arch/arm/src/stm32l1/chip.h index 4d0e326dc49..b0857c70503 100644 --- a/arch/arm/src/stm32/stm32_start.h +++ b/arch/arm/src/stm32l1/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_start.h + * arch/arm/src/stm32l1/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_START_H -#define __ARCH_ARM_SRC_STM32_STM32_START_H +#ifndef __ARCH_ARM_SRC_STM32L1_CHIP_H +#define __ARCH_ARM_SRC_STM32L1_CHIP_H /**************************************************************************** * Included Files @@ -29,21 +29,31 @@ #include -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" /**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after - * clocking and memory have been configured but before caches have been - * enabled and before any devices have been initialized. - * + * Pre-processor Definitions ****************************************************************************/ -void stm32_boardinitialize(void); +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_START_H */ +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32L1_CHIP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..bbe24f67a2c --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..9bbf21f2281 --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_aes.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h index c68fbc44d66..101ad5e19c4 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_aes.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h index 49dd7919b22..903605e60af 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h index b1c2ba9ce83..4a59b4c86ca 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h index 9211c8c64be..75294a51a74 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h index 0217a9a79d9..c557971f1a3 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h index 3e6dfa2ddbe..9cba220f8c2 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lowputc.h b/arch/arm/src/stm32l1/stm32.h similarity index 54% rename from arch/arm/src/stm32/stm32_lowputc.h rename to arch/arm/src/stm32l1/stm32.h index 76629be9c54..2aed55b33ca 100644 --- a/arch/arm/src/stm32/stm32_lowputc.h +++ b/arch/arm/src/stm32l1/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.h + * arch/arm/src/stm32l1/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,47 +20,50 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ #include "chip.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" #endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * Called at the very beginning of _start. - * Performs low level initialization of serial console. - * - ****************************************************************************/ - -void stm32_lowsetup(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32l1/stm32_rcc.c b/arch/arm/src/stm32l1/stm32_rcc.c new file mode 100644 index 00000000000..044d6aea475 --- /dev/null +++ b/arch/arm/src/stm32l1/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32l15xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32l15xxx_alarm.h b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_alarm.h rename to arch/arm/src/stm32l1/stm32l15xxx_alarm.h index 52267bf83c0..1d5e789cec9 100644 --- a/arch/arm/src/stm32/stm32l15xxx_alarm.h +++ b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_alarm.h + * arch/arm/src/stm32l1/stm32l15xxx_alarm.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xxx_rcc.c b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_rcc.c rename to arch/arm/src/stm32l1/stm32l15xxx_rcc.c index 043e46beca3..f7f08c0f656 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rcc.c +++ b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rcc.c + * arch/arm/src/stm32l1/stm32l15xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/Kconfig b/boards/Kconfig index bf39f97fd5b..ba2cb60b87f 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -4486,52 +4486,52 @@ if ARCH_BOARD_PIC32CZCA70_CURIOSITY source "boards/arm/samv7/pic32czca70-curiosity/Kconfig" endif if ARCH_BOARD_B_G474E_DPOW1 -source "boards/arm/stm32/b-g474e-dpow1/Kconfig" +source "boards/arm/stm32g4/b-g474e-dpow1/Kconfig" endif if ARCH_BOARD_B_G431B_ESC1 -source "boards/arm/stm32/b-g431b-esc1/Kconfig" +source "boards/arm/stm32g4/b-g431b-esc1/Kconfig" endif if ARCH_BOARD_NUCLEO_G431KB -source "boards/arm/stm32/nucleo-g431kb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431kb/Kconfig" endif if ARCH_BOARD_NUCLEO_G431RB -source "boards/arm/stm32/nucleo-g431rb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431rb/Kconfig" endif if ARCH_BOARD_B_L072Z_LRWAN1 -source "boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig" +source "boards/arm/stm32l0/b-l072z-lrwan1/Kconfig" endif if ARCH_BOARD_NUCLEO_F072RB -source "boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig" +source "boards/arm/stm32f0/nucleo-f072rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F091RC -source "boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig" +source "boards/arm/stm32f0/nucleo-f091rc/Kconfig" endif if ARCH_BOARD_NUCLEO_G070RB -source "boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g070rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G071RB -source "boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G0B1RE -source "boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig" +source "boards/arm/stm32g0/nucleo-g0b1re/Kconfig" endif if ARCH_BOARD_NUCLEO_L073RZ -source "boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig" +source "boards/arm/stm32l0/nucleo-l073rz/Kconfig" endif if ARCH_BOARD_STM32F051_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f051-discovery/Kconfig" endif if ARCH_BOARD_STM32L0538_DISCO -source "boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig" +source "boards/arm/stm32l0/stm32l0538-disco/Kconfig" endif if ARCH_BOARD_STM32F072_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f072-discovery/Kconfig" endif if ARCH_BOARD_NUCLEO_C071RB -source "boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig" +source "boards/arm/stm32c0/nucleo-c071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_C092RC -source "boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig" +source "boards/arm/stm32c0/nucleo-c092rc/Kconfig" endif if ARCH_BOARD_NUCLEO_F722ZE source "boards/arm/stm32f7/nucleo-f722ze/Kconfig" @@ -4651,151 +4651,151 @@ if ARCH_BOARD_NUCLEO_WB55RG source "boards/arm/stm32wb/nucleo-wb55rg/Kconfig" endif if ARCH_BOARD_AXOLOTI -source "boards/arm/stm32/axoloti/Kconfig" +source "boards/arm/stm32f4/axoloti/Kconfig" endif if ARCH_BOARD_CLICKER2_STM32 -source "boards/arm/stm32/clicker2-stm32/Kconfig" +source "boards/arm/stm32f4/clicker2-stm32/Kconfig" endif if ARCH_BOARD_CLOUDCTRL -source "boards/arm/stm32/cloudctrl/Kconfig" +source "boards/arm/stm32f1/cloudctrl/Kconfig" endif if ARCH_BOARD_EMW3162 -source "boards/arm/stm32/emw3162/Kconfig" +source "boards/arm/stm32f2/emw3162/Kconfig" endif if ARCH_BOARD_FIRE_STM32 -source "boards/arm/stm32/fire-stm32v2/Kconfig" +source "boards/arm/stm32f1/fire-stm32v2/Kconfig" endif if ARCH_BOARD_HYMINI_STM32V -source "boards/arm/stm32/hymini-stm32v/Kconfig" +source "boards/arm/stm32f1/hymini-stm32v/Kconfig" endif if ARCH_BOARD_MAPLE -source "boards/arm/stm32/maple/Kconfig" +source "boards/arm/stm32f1/maple/Kconfig" endif if ARCH_BOARD_ET_STM32_STAMP -source "boards/arm/stm32/et-stm32-stamp/Kconfig" +source "boards/arm/stm32f1/et-stm32-stamp/Kconfig" endif if ARCH_BOARD_MIKROE_STM32F4 -source "boards/arm/stm32/mikroe-stm32f4/Kconfig" +source "boards/arm/stm32f4/mikroe-stm32f4/Kconfig" endif if ARCH_BOARD_NUCLEO_F103RB -source "boards/arm/stm32/nucleo-f103rb/Kconfig" +source "boards/arm/stm32f1/nucleo-f103rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F207ZG -source "boards/arm/stm32/nucleo-f207zg/Kconfig" +source "boards/arm/stm32f2/nucleo-f207zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F302R8 -source "boards/arm/stm32/nucleo-f302r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f302r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F303RE -source "boards/arm/stm32/nucleo-f303re/Kconfig" +source "boards/arm/stm32f3/nucleo-f303re/Kconfig" endif if ARCH_BOARD_NUCLEO_F303ZE -source "boards/arm/stm32/nucleo-f303ze/Kconfig" +source "boards/arm/stm32f3/nucleo-f303ze/Kconfig" endif if ARCH_BOARD_NUCLEO_F334R8 -source "boards/arm/stm32/nucleo-f334r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f334r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F410RB -source "boards/arm/stm32/nucleo-f410rb/Kconfig" +source "boards/arm/stm32f4/nucleo-f410rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F412ZG -source "boards/arm/stm32/nucleo-f412zg/Kconfig" +source "boards/arm/stm32f4/nucleo-f412zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F446RE -source "boards/arm/stm32/nucleo-f446re/Kconfig" +source "boards/arm/stm32f4/nucleo-f446re/Kconfig" endif if ARCH_BOARD_NUCLEO_F401RE -source "boards/arm/stm32/nucleo-f401re/Kconfig" +source "boards/arm/stm32f4/nucleo-f401re/Kconfig" endif if ARCH_BOARD_NUCLEO_F411RE -source "boards/arm/stm32/nucleo-f411re/Kconfig" +source "boards/arm/stm32f4/nucleo-f411re/Kconfig" endif if ARCH_BOARD_STM32F401RC_RS485 -source "boards/arm/stm32/stm32f401rc-rs485/Kconfig" +source "boards/arm/stm32f4/stm32f401rc-rs485/Kconfig" endif if ARCH_BOARD_NUCLEO_F429ZI -source "boards/arm/stm32/nucleo-f429zi/Kconfig" +source "boards/arm/stm32f4/nucleo-f429zi/Kconfig" endif if ARCH_BOARD_NUCLEO_L152RE -source "boards/arm/stm32/nucleo-l152re/Kconfig" +source "boards/arm/stm32l1/nucleo-l152re/Kconfig" endif if ARCH_BOARD_ODRIVE36 -source "boards/arm/stm32/odrive36/Kconfig" +source "boards/arm/stm32f4/odrive36/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32E407 -source "boards/arm/stm32/olimex-stm32-e407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-e407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H405 -source "boards/arm/stm32/olimex-stm32-h405/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h405/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H407 -source "boards/arm/stm32/olimex-stm32-h407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P107 -source "boards/arm/stm32/olimex-stm32-p107/Kconfig" +source "boards/arm/stm32f1/olimex-stm32-p107/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P207 -source "boards/arm/stm32/olimex-stm32-p207/Kconfig" +source "boards/arm/stm32f2/olimex-stm32-p207/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P407 -source "boards/arm/stm32/olimex-stm32-p407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-p407/Kconfig" endif if ARCH_BOARD_OLIMEXINO_STM32 -source "boards/arm/stm32/olimexino-stm32/Kconfig" +source "boards/arm/stm32f1/olimexino-stm32/Kconfig" endif if ARCH_BOARD_OMNIBUSF4 -source "boards/arm/stm32/omnibusf4/Kconfig" +source "boards/arm/stm32f4/omnibusf4/Kconfig" endif if ARCH_BOARD_PHOTON -source "boards/arm/stm32/photon/Kconfig" +source "boards/arm/stm32f2/photon/Kconfig" endif if ARCH_BOARD_SHENZHOU -source "boards/arm/stm32/shenzhou/Kconfig" +source "boards/arm/stm32f1/shenzhou/Kconfig" endif if ARCH_BOARD_STM3210E_EVAL -source "boards/arm/stm32/stm3210e-eval/Kconfig" +source "boards/arm/stm32f1/stm3210e-eval/Kconfig" endif if ARCH_BOARD_STM3220G_EVAL -source "boards/arm/stm32/stm3220g-eval/Kconfig" +source "boards/arm/stm32f2/stm3220g-eval/Kconfig" endif if ARCH_BOARD_STM3240G_EVAL -source "boards/arm/stm32/stm3240g-eval/Kconfig" +source "boards/arm/stm32f4/stm3240g-eval/Kconfig" endif if ARCH_BOARD_STM32_TINY -source "boards/arm/stm32/stm32_tiny/Kconfig" +source "boards/arm/stm32f1/stm32_tiny/Kconfig" endif if ARCH_BOARD_STM32_BUTTERFLY2 -source "boards/arm/stm32/stm32butterfly2/Kconfig" +source "boards/arm/stm32f1/stm32butterfly2/Kconfig" endif if ARCH_BOARD_STM32F103_MINIMUM -source "boards/arm/stm32/stm32f103-minimum/Kconfig" +source "boards/arm/stm32f1/stm32f103-minimum/Kconfig" endif if ARCH_BOARD_STM32F411_MINIMUM -source "boards/arm/stm32/stm32f411-minimum/Kconfig" +source "boards/arm/stm32f4/stm32f411-minimum/Kconfig" endif if ARCH_BOARD_STM32F334_DISCO -source "boards/arm/stm32/stm32f334-disco/Kconfig" +source "boards/arm/stm32f3/stm32f334-disco/Kconfig" endif if ARCH_BOARD_STM32F3_DISCOVERY -source "boards/arm/stm32/stm32f3discovery/Kconfig" +source "boards/arm/stm32f3/stm32f3discovery/Kconfig" endif if ARCH_BOARD_STM32F411E_DISCO -source "boards/arm/stm32/stm32f411e-disco/Kconfig" +source "boards/arm/stm32f4/stm32f411e-disco/Kconfig" endif if ARCH_BOARD_STM32F429I_DISCO -source "boards/arm/stm32/stm32f429i-disco/Kconfig" +source "boards/arm/stm32f4/stm32f429i-disco/Kconfig" endif if ARCH_BOARD_STM32F4_DISCOVERY -source "boards/arm/stm32/stm32f4discovery/Kconfig" +source "boards/arm/stm32f4/stm32f4discovery/Kconfig" endif if ARCH_BOARD_STM32L_DISCOVERY -source "boards/arm/stm32/stm32ldiscovery/Kconfig" +source "boards/arm/stm32l1/stm32ldiscovery/Kconfig" endif if ARCH_BOARD_STM32VL_DISCOVERY -source "boards/arm/stm32/stm32vldiscovery/Kconfig" +source "boards/arm/stm32f1/stm32vldiscovery/Kconfig" endif if ARCH_BOARD_VIEWTOOL_STM32F107 -source "boards/arm/stm32/viewtool-stm32f107/Kconfig" +source "boards/arm/stm32f1/viewtool-stm32f107/Kconfig" endif if ARCH_BOARD_OLIMEX_STRP711 source "boards/arm/str71x/olimex-strp711/Kconfig" diff --git a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt deleted file mode 100644 index 3444cc83430..00000000000 --- a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f103rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt deleted file mode 100644 index 9fe17612d17..00000000000 --- a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f207zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs deleted file mode 100644 index a0ae3c3954b..00000000000 --- a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f207zg/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt deleted file mode 100644 index 62e41b7cca4..00000000000 --- a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f302r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs deleted file mode 100644 index d863be25bf5..00000000000 --- a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f302r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt b/boards/arm/stm32/nucleo-f303re/CMakeLists.txt deleted file mode 100644 index fb2ec37234e..00000000000 --- a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt b/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt deleted file mode 100644 index 0892584b294..00000000000 --- a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303ze/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt deleted file mode 100644 index ef3be834441..00000000000 --- a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f334r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs deleted file mode 100644 index 24b7d458136..00000000000 --- a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f334r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt b/boards/arm/stm32/nucleo-f401re/CMakeLists.txt deleted file mode 100644 index fc3725e660d..00000000000 --- a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f401re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt deleted file mode 100644 index 9c873cd8765..00000000000 --- a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f410rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt b/boards/arm/stm32/nucleo-f411re/CMakeLists.txt deleted file mode 100644 index 53fe0025e44..00000000000 --- a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f411re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt deleted file mode 100644 index df7b29ff230..00000000000 --- a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f412zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt b/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt deleted file mode 100644 index 5d868f0710b..00000000000 --- a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f429zi/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt b/boards/arm/stm32/nucleo-f446re/CMakeLists.txt deleted file mode 100644 index 5b0efd703eb..00000000000 --- a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f446re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt deleted file mode 100644 index ce86b7005c1..00000000000 --- a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431kb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt deleted file mode 100644 index c8eda596831..00000000000 --- a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt b/boards/arm/stm32/nucleo-g474re/CMakeLists.txt deleted file mode 100644 index 7fcedbbbecb..00000000000 --- a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g474re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs b/boards/arm/stm32/nucleo-g474re/scripts/Make.defs deleted file mode 100644 index 977ae0d4707..00000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g474re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt b/boards/arm/stm32/nucleo-l152re/CMakeLists.txt deleted file mode 100644 index 5a90572fa08..00000000000 --- a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-l152re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs b/boards/arm/stm32/nucleo-l152re/scripts/Make.defs deleted file mode 100644 index 2eb2354673a..00000000000 --- a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-l152re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt deleted file mode 100644 index 33d4a705181..00000000000 --- a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt deleted file mode 100644 index 58cb6b36828..00000000000 --- a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt deleted file mode 100644 index 37624d8016f..00000000000 --- a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs deleted file mode 100644 index 6dae53fb984..00000000000 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt deleted file mode 100644 index 714fc64c28c..00000000000 --- a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt deleted file mode 100644 index e80a16fed32..00000000000 --- a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt deleted file mode 100644 index 9932d6545d5..00000000000 --- a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt b/boards/arm/stm32/olimexino-stm32/CMakeLists.txt deleted file mode 100644 index bf93e02b885..00000000000 --- a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimexino-stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/omnibusf4/CMakeLists.txt b/boards/arm/stm32/omnibusf4/CMakeLists.txt deleted file mode 100644 index bf326c7306a..00000000000 --- a/boards/arm/stm32/omnibusf4/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/omnibusf4/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/shenzhou/CMakeLists.txt b/boards/arm/stm32/shenzhou/CMakeLists.txt deleted file mode 100644 index afc3a611633..00000000000 --- a/boards/arm/stm32/shenzhou/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/shenzhou/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt b/boards/arm/stm32/stm3210e-eval/CMakeLists.txt deleted file mode 100644 index 7bbea8e4a97..00000000000 --- a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3210e-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt b/boards/arm/stm32/stm3220g-eval/CMakeLists.txt deleted file mode 100644 index 70278d3238c..00000000000 --- a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3220g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs b/boards/arm/stm32/stm3220g-eval/scripts/Make.defs deleted file mode 100644 index f0aa8af0b8e..00000000000 --- a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3220g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt b/boards/arm/stm32/stm3240g-eval/CMakeLists.txt deleted file mode 100644 index 823f2be9fe8..00000000000 --- a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3240g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32/stm3240g-eval/scripts/Make.defs deleted file mode 100644 index 091ebb2629a..00000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32_tiny/CMakeLists.txt b/boards/arm/stm32/stm32_tiny/CMakeLists.txt deleted file mode 100644 index 6b35bfde309..00000000000 --- a/boards/arm/stm32/stm32_tiny/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32_tiny/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt b/boards/arm/stm32/stm32butterfly2/CMakeLists.txt deleted file mode 100644 index 9daf994ef14..00000000000 --- a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32butterfly2/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt deleted file mode 100644 index d4b2e558d30..00000000000 --- a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f103-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt b/boards/arm/stm32/stm32f334-disco/CMakeLists.txt deleted file mode 100644 index 1d87be10fd0..00000000000 --- a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f334-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32/stm32f334-disco/scripts/Make.defs deleted file mode 100644 index 3312eb47258..00000000000 --- a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f334-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt b/boards/arm/stm32/stm32f3discovery/CMakeLists.txt deleted file mode 100644 index b5910c678d9..00000000000 --- a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f3discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32/stm32f3discovery/scripts/Make.defs deleted file mode 100644 index f4a90c1997c..00000000000 --- a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f3discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt b/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt deleted file mode 100644 index 0c3a3b0299f..00000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt deleted file mode 100644 index cc4e5162529..00000000000 --- a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt b/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt deleted file mode 100644 index 884177caaef..00000000000 --- a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411e-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt b/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt deleted file mode 100644 index 7e51cbd70df..00000000000 --- a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f429i-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld b/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld deleted file mode 100644 index db9d9db676a..00000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32/stm32f4discovery/scripts/Make.defs deleted file mode 100644 index 109235fb9cd..00000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt deleted file mode 100644 index bde3559ad0c..00000000000 --- a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32ldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt deleted file mode 100644 index 0b290a9db73..00000000000 --- a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32vldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt b/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt deleted file mode 100644 index 4fc77f37f5d..00000000000 --- a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt b/boards/arm/stm32l1/common/CMakeLists.txt similarity index 86% rename from boards/arm/stm32/et-stm32-stamp/CMakeLists.txt rename to boards/arm/stm32l1/common/CMakeLists.txt index d1c3d364013..901c509ec76 100644 --- a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt +++ b/boards/arm/stm32l1/common/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/et-stm32-stamp/CMakeLists.txt +# boards/arm/stm32l1/common/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -20,4 +20,6 @@ # # ############################################################################## -add_subdirectory(src) +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32l1/common/Kconfig b/boards/arm/stm32l1/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32l1/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32l1/common/Makefile similarity index 51% rename from boards/arm/stm32/nucleo-f303re/scripts/Make.defs rename to boards/arm/stm32l1/common/Makefile index eb1b16a4ac2..8b3122d2c70 100644 --- a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs +++ b/boards/arm/stm32l1/common/Makefile @@ -1,5 +1,5 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303re/scripts/Make.defs +############################################################################# +# boards/arm/stm32l1/common/Makefile # # SPDX-License-Identifier: Apache-2.0 # @@ -18,24 +18,21 @@ # License for the specific language governing permissions and limitations # under the License. # -############################################################################ +############################################################################# -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs +include $(TOPDIR)/Make.defs -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ +DEPPATH += --dep-path board -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/hymini-stm32v/CMakeLists.txt rename to boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt index 7cc2354980b..199de2f567a 100644 --- a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt +++ b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/hymini-stm32v/CMakeLists.txt +# boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/Kconfig b/boards/arm/stm32l1/nucleo-l152re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-l152re/Kconfig rename to boards/arm/stm32l1/nucleo-l152re/Kconfig diff --git a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig rename to boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig index bbbb2ac2407..73ee4c8eb4e 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig +++ b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l152re" CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RE=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig rename to boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig index 19e97ac9e09..3b73a53c8df 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig +++ b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l152re" CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RE=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/nucleo-l152re/include/board.h b/boards/arm/stm32l1/nucleo-l152re/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-l152re/include/board.h rename to boards/arm/stm32l1/nucleo-l152re/include/board.h index 1c9ff4c06a5..a8e89cabee0 100644 --- a/boards/arm/stm32/nucleo-l152re/include/board.h +++ b/boards/arm/stm32l1/nucleo-l152re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/include/board.h + * boards/arm/stm32l1/nucleo-l152re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f303ze/scripts/Make.defs rename to boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs index fba0285e373..656e9afe070 100644 --- a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f303ze/scripts/Make.defs +# boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/scripts/ld.script b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-l152re/scripts/ld.script rename to boards/arm/stm32l1/nucleo-l152re/scripts/ld.script index 51325adba93..747f91401b8 100644 --- a/boards/arm/stm32/nucleo-l152re/scripts/ld.script +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/scripts/ld.script + * boards/arm/stm32l1/nucleo-l152re/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt rename to boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt index c8bbc27e2fe..9177895b7e4 100644 --- a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt +++ b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt +# boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/src/Make.defs b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-l152re/src/Make.defs rename to boards/arm/stm32l1/nucleo-l152re/src/Make.defs index 3eafd51d2e9..b1d374b5b3e 100644 --- a/boards/arm/stm32/nucleo-l152re/src/Make.defs +++ b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-l152re/src/Make.defs +# boards/arm/stm32l1/nucleo-l152re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h rename to boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h index dbdcb8cbf1a..7533f5860f9 100644 --- a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h +++ b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h + * boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c index 69c14c5f96f..dcab65cab6d 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_boot.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c index f9b3cd58433..3545cdbafa0 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_boot.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c index 47366db118c..645eac093f8 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c index 7b8052671c0..a07de22023d 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_spi.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c index 5d59d781d63..66b5dae214d 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spi.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c index c08c068b2fb..9683f10cc4c 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c index 4ed85198d21..bb9d60e5a2c 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/fire-stm32v2/CMakeLists.txt rename to boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt index a7c4eb1ccad..86a0d6e5493 100644 --- a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt +++ b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/fire-stm32v2/CMakeLists.txt +# boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/Kconfig b/boards/arm/stm32l1/stm32ldiscovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32ldiscovery/Kconfig rename to boards/arm/stm32l1/stm32ldiscovery/Kconfig diff --git a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig rename to boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig index 9022ce804f8..c965f4dc993 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32ldiscovery" CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RB=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig rename to boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig index 0ed417736d6..e07f7bfeadc 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32ldiscovery" CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RB=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/stm32ldiscovery/include/board.h b/boards/arm/stm32l1/stm32ldiscovery/include/board.h similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/include/board.h rename to boards/arm/stm32l1/stm32ldiscovery/include/board.h index a36765cc66e..9e1c58d534c 100644 --- a/boards/arm/stm32/stm32ldiscovery/include/board.h +++ b/boards/arm/stm32l1/stm32ldiscovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/include/board.h + * boards/arm/stm32l1/stm32ldiscovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm32ldiscovery/scripts/Make.defs rename to boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs index d9b35b396fa..ac42a713715 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32ldiscovery/scripts/Make.defs +# boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld index bb8c62933c6..184ed288509 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld index 81b7157ce80..d295e75c07a 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt rename to boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt index feae2b53ca1..a496f64f86b 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt +++ b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt +# boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/src/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs similarity index 96% rename from boards/arm/stm32/stm32ldiscovery/src/Make.defs rename to boards/arm/stm32l1/stm32ldiscovery/src/Make.defs index 0a07db0a932..f483afc2b24 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/Make.defs +++ b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32ldiscovery/src/Make.defs +# boards/arm/stm32l1/stm32ldiscovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c index e251d0f2ead..e62f9ed1484 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c index 701fdbd303c..751e937f799 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c index be3ff1616ed..ee512f314b3 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c index 15071e1fe40..3f0e1ffb331 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c index ff4119682da..379abcfa7bd 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c index 3857da41ec4..d18d9278bdd 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c index 7263febe7ea..3066e34f1d6 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c index 362209fa599..5c6555da521 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h index a3ef72b7265..7f1afcb12f9 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h + * boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/tools/ci/testlist/arm-08.dat b/tools/ci/testlist/arm-08.dat index dda347b33d8..b6354c5200c 100644 --- a/tools/ci/testlist/arm-08.dat +++ b/tools/ci/testlist/arm-08.dat @@ -1,10 +1,25 @@ -/arm/stm32/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32c0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f3/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32h7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32u5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32wb/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f2/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f3/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-09.dat b/tools/ci/testlist/arm-09.dat index cd9c27d5fdb..82448d0a9ab 100644 --- a/tools/ci/testlist/arm-09.dat +++ b/tools/ci/testlist/arm-09.dat @@ -1,12 +1,18 @@ -/arm/stm32/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l0/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l4/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l5/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-10.dat b/tools/ci/testlist/arm-10.dat index 1e45e9365cd..30d56951ccd 100644 --- a/tools/ci/testlist/arm-10.dat +++ b/tools/ci/testlist/arm-10.dat @@ -1,15 +1,15 @@ -/arm/stm32/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG -shenzhou:thttpd -/arm/stm32/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm3240g-eval:knxwm diff --git a/tools/ci/testlist/arm-11.dat b/tools/ci/testlist/arm-11.dat index 6af3cdbfa51..2564b8be8e0 100644 --- a/tools/ci/testlist/arm-11.dat +++ b/tools/ci/testlist/arm-11.dat @@ -1,18 +1,18 @@ -/arm/stm32/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG # Boards build by CMake diff --git a/tools/ci/testlist/arm-12.dat b/tools/ci/testlist/arm-12.dat index caf77554375..e9e1aa7a42b 100644 --- a/tools/ci/testlist/arm-12.dat +++ b/tools/ci/testlist/arm-12.dat @@ -1,11 +1,11 @@ -/arm/stm32/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm32f4discovery:winbuild -/arm/stm32/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG # cURL error 60 SSL certificate expired -stm32f4discovery:cxxtest diff --git a/tools/ci/testlist/macos.dat b/tools/ci/testlist/macos.dat index 70c05ee29db..6c442b5026a 100644 --- a/tools/ci/testlist/macos.dat +++ b/tools/ci/testlist/macos.dat @@ -3,7 +3,7 @@ # ARM -/arm/stm32/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/msys2.dat b/tools/ci/testlist/msys2.dat index 542b59af419..1996dff9c3c 100644 --- a/tools/ci/testlist/msys2.dat +++ b/tools/ci/testlist/msys2.dat @@ -3,9 +3,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/windows.dat b/tools/ci/testlist/windows.dat index ec54d4f82bb..15d7c21b1ae 100644 --- a/tools/ci/testlist/windows.dat +++ b/tools/ci/testlist/windows.dat @@ -2,9 +2,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG /arm/rp2040/raspberrypi-pico/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI