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36149b775e
Add an ICACHE section to the STM32H5 platform page. With CONFIG_STM32_ICACHE the OTP, read-only and EDATA flash areas are mapped non-cacheable with an MPU region, so they can be read like any other memory. The MPU is not applied in the HardFault and NMI handlers (HFNMIENA=0), so these areas must not be read from NMI or HardFault context: with the ICACHE enabled such a read raises a bus fault. Assisted-by: Claude:claude-sonnet-5-5 Signed-off-by: Ricardo Maurizio Paul <ricardopaul@geotab.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| hc | ||
| mips | ||
| misco | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| index.rst | ||