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d4201facd8
Several bugs made the MIPS32 cache functions unusable: - The range functions rounded the end address down instead of up and stopped before it, so the last line was never handled. A range within a single line started a loop that only ended when the address wrapped around 4 GB, which took seconds. - HIT_WRITEBACK_D was 0x15, which is Hit_Writeback_Inv_D. Hit Writeback D is 0x19. up_clean_dcache() now uses it and up_flush_dcache() uses Hit_Writeback_Inv_D. - The *_all functions used Hit operations over a KSEG0 range the size of the cache, which only affects lines caching that range. Use index operations instead: Index_Invalidate_I, Index_Writeback_Inv_D and, to discard the D-Cache, Index_Store_Tag_D with a zero tag. - With CONFIG_MIPS32_CACHE_AUTOINFO the line size was computed with a right shift instead of a left shift. - The CACHE_OP loop label was "1", the same label the callers use to skip the operation, and the branch delay slot was left to whatever instruction followed. - up_coherent_dcache() called up_invalidate_icache_all() even when it is not built. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||