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c2595870e5
MCAN controller keeps track of empty TX HW FIFO slots in priv->txfsem semaphore. The semaphore is incremented from TX complete interrupt and taken before new frame is inserted to the HW FIFO. There may be a situation when TX HW FIFO is not full but the semaphore is not yet incremented because the driver didn't handle the interrupt. I managed to reproduce this issue when sending large data chunks over CAN bus and keeping the buffers full for most of the transmission process. This situation leads to the debug assertion although technically it's not a big issue -> the sending function waits on the semaphore until it's posted by the interrupt handler. Moreover, the sanity checks should not be necessary because mcan_buffer_reserve function will take care of fixing the semaphore value if it doesn't match with the FIFO. The entire semaphore logic is a bit weird and probably not necessary. All we need to do is to check SAM_MCAN_TXFQS register if there is at least one free slot in the queue. But this would require a bigger SAMv7 MCAN rewrite, this is rather a hot fix. Signed-off-by: Michal Lenc <michallenc@seznam.cz> |
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