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c47d7151d7
The EIC7700X is not cache coherent. No device that moves data on its own snoops the harts' caches or is snooped by them, so a buffer handed to a device needs the cache maintained around the transfer. The harts are coherent with each other; it is DMA that is not. The RISC-V standard offers no way to do that here: the Zicbom extension this core does not implement is the portable answer, and there is no other. Maintenance is instead a store to the L3 controller carrying the physical address of a cache block. That store is the only operation the hardware offers: it writes back and invalidates together, so a block cannot be dropped without being written out first. Everything built on top is shaped by that, which is why a range being invalidated has to own whole blocks. The L3 is inclusive of the L1 data cache and back invalidates it, so one store per block maintains the whole hierarchy, with nothing to do per hart. The block size is 64 bytes, which is what makes the descriptor rules in the storage and network drivers what they are. Assisted-by: Claude:claude-opus-5 Signed-off-by: Justin Hammond <justin@dynam.ac> |
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