mirror of
https://github.com/apache/nuttx.git
synced 2026-10-07 22:35:22 +00:00
dc6e924a95
An enabled ICACHE does not manage write transactions: it flags cacheable writes as errors (ICACHE_SR.ERRF), and RM0481 8.4.5 recommends modifying the memory with the ICACHE disabled. On an STM32H563, erasing and programming a flash block with the ICACHE enabled leaves ICACHE_SR at 0x6 (BSYENDF and ERRF set). The ICACHE also keeps serving lines cached before the change. When the block had been read through the ICACHE just before it was programmed, up_progmem_write() failed its read-back check with -EIO: the flash held the new data, with no flash or ECC error flagged, but the read-back hit the cached erased data. up_progmem_eraseblock() fails its erased-range check the same way when programmed data of the block is cached. Disable the ICACHE for the duration of up_progmem_eraseblock() and up_progmem_write(), and enable it again afterwards if it was enabled on entry. Disabling it invalidates it, so the refill after re-enabling it sees the new flash content. If the ICACHE cannot be re-enabled because its invalidate times out, it is left disabled, which is safe but slower, and an error is logged. Assisted-by: Claude:claude-sonnet-5-5 Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Ricardo Maurizio Paul <ricardopaul@geotab.com> |
||
|---|---|---|
| .. | ||
| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||