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nuttx/arch/tricore/include
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zhangyu117 d2c91137e5 arch/tricore: cachecode donot depend on illd 
Replace the iLLD register structures (Ifx_CPU_PCON0/1/2, Ifx_CPU_DCON0/1/2)
and the IfxCpu_cfg.h cache-size/line-size macros in the cache path with
direct CSR accesses via tricore_mtcr()/tricore_mfcr() and locally defined
PCON/DCON bit masks.  Also switch __isync()/__dsync() to the UP_ISB()/
UP_DSB() barrier wrappers.

This removes the arch/tricore cache path's dependency on the Infineon
iLLD layer.  No behavior change.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-08-13 12:38:45 +02:00
..
tc4da arch/tricore: support tc4evb board. 2026-03-10 10:38:19 +01:00
tc397 arch/tricore: adjust arch-related irq.h 2026-03-10 10:38:19 +01:00
.gitignore
arch.h arch/tricore: add tricore_mtcr and tricore_mfcr macros 2026-08-13 12:38:45 +02:00
barriers.h arch/tricore: cachecode donot depend on illd 2026-08-13 12:38:45 +02:00
inttypes.h arch/tricore: Resolving gcc compilation warning 2026-01-15 11:37:12 +08:00
irq.h tricore: Add fpu init to open FZ trap. 2026-05-21 11:34:14 +08:00
limits.h arch/tricore: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
setjmp.h arch/tricore: Full implementation of setjmp and longjmp. 2026-05-22 00:38:02 +08:00
spinlock.h arch/tricore:use UP_DSB, UP_DMB, UP_ISB as barrier standard API 2025-01-20 20:13:07 +08:00
syscall.h arch/tricore: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
types.h arch/tricore: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00