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d4d4db5bb1
Replace the iLLD helpers IfxCpu_resetAndStartCounters() and IfxCpu_getClockCounter() in the performance-counter path with direct CSR accesses via tricore_mtcr()/tricore_mfcr(). tricore_reset_ccnt() disables the CPU cycle counter (CPU_CCTRL), clears CPU_CCNT, then re-enables it; up_perf_gettime() reads CPU_CCNT directly. This removes the arch/tricore perf path's dependency on the Infineon iLLD layer. No behavior change. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com> |
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