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ec7ee53f6f
Expose the RTL8730E general-purpose UARTs through the shared Ameba serial driver (arch/arm/src/common/ameba/ameba_uart.c) by adding the chip-specific glue, build wiring and a board port table. The change is gated by CONFIG_AMEBA_UART (default disabled); the LOG-UART keeps the console and /dev/ttyS0. Chip glue (ameba_uart_chip.h) supplies the three UART controller register bases, GIC IRQ numbers (SPI 50/51/52 -> NuttX IRQ 82/83/84), APB clock masks and pin-mux codes. The board registers UART0-2 as /dev/ttyS1-3 at 115200 8N1; UART3 is reserved for Bluetooth. Pads are picked from the EVB break-out (the UART crossbar maps each controller to many pads, so this is purely a board choice). Also fix an RX-timeout interrupt storm in the shared driver: the RX-timeout status (LSR bit9) is latched and is not cleared by draining the RX FIFO, so on a level-triggered GIC (RTL8730E) the ISR must explicitly write TOICF, matching the vendor SDK serial_api.c. The extra register write is harmless on the NVIC-based M33 Ameba parts and was regression-tested on them. Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn> Assisted-by: Claude <noreply@anthropic.com> |
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| .. | ||
| arm | ||
| arm64 | ||
| avr | ||
| dummy | ||
| hc/m9s12 | ||
| mips | ||
| misoc/lm32/misoc | ||
| or1k/mor1kx/or1k | ||
| renesas | ||
| risc-v | ||
| sim/sim/sim | ||
| sparc | ||
| tricore | ||
| x86/qemu/qemu-i486 | ||
| x86_64/qemu/qemu-intel64 | ||
| xtensa | ||
| z16/z16f/z16f2800100zcog | ||
| z80 | ||
| .gitignore | ||
| Board.mk | ||
| boardctl.c | ||
| CMakeLists.txt | ||
| dummy.c | ||
| Kconfig | ||
| Makefile | ||