mirror of
https://github.com/apache/nuttx.git
synced 2026-08-15 17:33:18 +00:00
1a8fba827a
This patch adds definitions for listed chips. No other changes are needed as the chips are similar to the previously supported AVR128DA28 and all that is needed is some definitions for extra peripherals.
318 lines
12 KiB
C
318 lines
12 KiB
C
/****************************************************************************
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* arch/avr/include/avrdx/irq.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_AVR_INCLUDE_AVRDX_IRQ_H
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#define __ARCH_AVR_INCLUDE_AVRDX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/irq.h>
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#include <arch/avr/avr.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* AVRnDx interrupt vectors other than vector 0, the reset vector, are
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* assigned here:
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*/
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#if defined(CONFIG_ARCH_CHIP_AVR128DA28)
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# define AVRDX_IRQ_NMI 0 /* Non-maskable interrupt */
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# define AVRDX_IRQ_BOD_VLM 1 /* BOD interrupt */
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# define AVRDX_IRQ_RTC_CNT 2 /* RTC and periodic interrupt */
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# define AVRDX_IRQ_RTC_PIT 3
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# define AVRDX_IRQ_CCL_CCL 4 /* CCL */
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# define AVRDX_IRQ_PORTA_PORT 5 /* PORTA interrupts */
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# define AVRDX_IRQ_TCA0_LUNF 6 /* TIMER A0 Low byte underflow */
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# define AVRDX_IRQ_TCA0_OVF 6
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# define AVRDX_IRQ_TCA0_HUNF 7 /* TIMER A0 High byte underflow */
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# define AVRDX_IRQ_TCA0_CMP0 8 /* TIMER A0 compare match 0 */
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# define AVRDX_IRQ_TCA0_LCMP0 8 /* TIMER A0 Low byte compare match 0 */
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# define AVRDX_IRQ_TCA0_CMP1 9
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# define AVRDX_IRQ_TCA0_LCMP1 9
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# define AVRDX_IRQ_TCA0_CMP2 10
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# define AVRDX_IRQ_TCA0_LCMP2 10
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# define AVRDX_IRQ_TCB0_INT 11
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# define AVRDX_IRQ_TCB1_INT 12
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# define AVRDX_IRQ_TCD0_OVF 13
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# define AVRDX_IRQ_TCD0_TRIG 14
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# define AVRDX_IRQ_TWI0_TWIS 15 /* TWI client interrupt */
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# define AVRDX_IRQ_TWI0_TWIM 16 /* TWI host interrupt */
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# define AVRDX_IRQ_SPI0_INT 17
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# define AVRDX_IRQ_USART0_RXC 18
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# define AVRDX_IRQ_USART0_DRE 19
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# define AVRDX_IRQ_USART0_TXC 20
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# define AVRDX_IRQ_PORTD_PORT 21
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# define AVRDX_IRQ_AC0_AC 22 /* AC0 analog comparator interrupt */
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# define AVRDX_IRQ_ADC0_RESRDY 23 /* ADC0 result ready */
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# define AVRDX_IRQ_ADC0_WCMP 24 /* ADC0 Window compare interrupt */
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# define AVRDX_IRQ_ZCD0_ZCD 25 /* Zero-cross interrupt */
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# define AVRDX_IRQ_PTC_PTC 26 /* Peripheral touch controller interrupt */
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# define AVRDX_IRQ_AC1_AC 27
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# define AVRDX_IRQ_PORTC_PORT 28
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# define AVRDX_IRQ_TCB2_INT 29
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# define AVRDX_IRQ_USART1_RXC 30
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# define AVRDX_IRQ_USART1_DRE 31
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# define AVRDX_IRQ_USART1_TXC 32
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# define AVRDX_IRQ_PORTF_PORT 33
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# define AVRDX_IRQ_NVMCTRL_EE 34 /* NVM controller EEPROM ready interrupt */
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# define AVRDX_IRQ_SPI1_INT 35
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# define AVRDX_IRQ_USART2_RXC 36
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# define AVRDX_IRQ_USART2_DRE 37
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# define AVRDX_IRQ_USART2_TXC 38
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# define AVRDX_IRQ_AC2_AC 39
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# define NR_IRQS 40
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# define AVR_PC_SIZE 16
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# define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes),
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* 32B registers + 1B SREG + 2B PC + 2B SP (?)
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* +1B RAMPZ
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*/
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# if defined(CONFIG_AVR_HAS_RAMPZ)
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# define AVR_HAS_RAMPZ
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# else
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# error CONFIG_AVR_HAS_RAMPZ is supposed to be set for this chip
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# endif
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#elif defined(CONFIG_ARCH_CHIP_AVR128DA64)
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# define AVRDX_IRQ_NMI 0 /* Non-maskable interrupt */
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# define AVRDX_IRQ_BOD_VLM 1 /* BOD interrupt */
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# define AVRDX_IRQ_RTC_CNT 2 /* RTC and periodic interrupt */
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# define AVRDX_IRQ_RTC_PIT 3
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# define AVRDX_IRQ_CCL_CCL 4 /* CCL */
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# define AVRDX_IRQ_PORTA_PORT 5 /* PORTA interrupts */
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# define AVRDX_IRQ_TCA0_LUNF 6 /* TIMER A0 Low byte underflow */
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# define AVRDX_IRQ_TCA0_OVF 6
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# define AVRDX_IRQ_TCA0_HUNF 7 /* TIMER A0 High byte underflow */
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# define AVRDX_IRQ_TCA0_CMP0 8 /* TIMER A0 compare match 0 */
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# define AVRDX_IRQ_TCA0_LCMP0 8 /* TIMER A0 Low byte compare match 0 */
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# define AVRDX_IRQ_TCA0_CMP1 9
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# define AVRDX_IRQ_TCA0_LCMP1 9
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# define AVRDX_IRQ_TCA0_CMP2 10
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# define AVRDX_IRQ_TCA0_LCMP2 10
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# define AVRDX_IRQ_TCB0_INT 11
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# define AVRDX_IRQ_TCB1_INT 12
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# define AVRDX_IRQ_TCD0_OVF 13
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# define AVRDX_IRQ_TCD0_TRIG 14
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# define AVRDX_IRQ_TWI0_TWIS 15 /* TWI client interrupt */
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# define AVRDX_IRQ_TWI0_TWIM 16 /* TWI host interrupt */
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# define AVRDX_IRQ_SPI0_INT 17
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# define AVRDX_IRQ_USART0_RXC 18
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# define AVRDX_IRQ_USART0_DRE 19
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# define AVRDX_IRQ_USART0_TXC 20
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# define AVRDX_IRQ_PORTD_PORT 21
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# define AVRDX_IRQ_AC0_AC 22 /* AC0 analog comparator interrupt */
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# define AVRDX_IRQ_ADC0_RESRDY 23 /* ADC0 result ready */
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# define AVRDX_IRQ_ADC0_WCMP 24 /* ADC0 Window compare interrupt */
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# define AVRDX_IRQ_ZCD0_ZCD 25 /* Zero-cross interrupt */
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# define AVRDX_IRQ_PTC_PTC 26 /* Peripheral touch controller interrupt */
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# define AVRDX_IRQ_AC1_AC 27
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# define AVRDX_IRQ_PORTC_PORT 28
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# define AVRDX_IRQ_TCB2_INT 29
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# define AVRDX_IRQ_USART1_RXC 30
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# define AVRDX_IRQ_USART1_DRE 31
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# define AVRDX_IRQ_USART1_TXC 32
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# define AVRDX_IRQ_PORTF_PORT 33
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# define AVRDX_IRQ_NVMCTRL_EE 34 /* NVM controller EEPROM ready interrupt */
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# define AVRDX_IRQ_SPI1_INT 35
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# define AVRDX_IRQ_USART2_RXC 36
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# define AVRDX_IRQ_USART2_DRE 37
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# define AVRDX_IRQ_USART2_TXC 38
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# define AVRDX_IRQ_AC2_AC 39
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# define AVRDX_IRQ_TCB3_INT 40
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# define AVRDX_IRQ_TWI1_TWIS 41
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# define AVRDX_IRQ_TWI1_TWIM 42
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# define AVRDX_IRQ_PORTB_PORT 43
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# define AVRDX_IRQ_PORTE_PORT 44
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# define AVRDX_IRQ_TCA1_LUNF 45
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# define AVRDX_IRQ_TCA1_OVF 45
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# define AVRDX_IRQ_TCA1_HUNF 46
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# define AVRDX_IRQ_TCA1_CMP0 47
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# define AVRDX_IRQ_TCA1_LCMP0 47
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# define AVRDX_IRQ_TCA1_CMP1 48
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# define AVRDX_IRQ_TCA1_LCMP1 48
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# define AVRDX_IRQ_TCA1_CMP2 49
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# define AVRDX_IRQ_TCA1_LCMP2 49
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# define AVRDX_IRQ_ZCD1_ZCD 50
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# define AVRDX_IRQ_USART3_RXC 51
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# define AVRDX_IRQ_USART3_DRE 52
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# define AVRDX_IRQ_USART3_TXC 53
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# define AVRDX_IRQ_USART4_RXC 54
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# define AVRDX_IRQ_USART4_DRE 55
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# define AVRDX_IRQ_USART4_TXC 56
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# define AVRDX_IRQ_PORTG_PORT 57
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# define AVRDX_IRQ_ZCD2_ZCD 58
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# define AVRDX_IRQ_TCB4_INT 59
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# define AVRDX_IRQ_USART5_RXC 60
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# define AVRDX_IRQ_USART5_DRE 61
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# define AVRDX_IRQ_USART5_TXC 62
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# define NR_IRQS 63
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# define AVR_PC_SIZE 16
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# define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes),
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* 32B registers + 1B SREG + 2B PC + 2B SP
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* +1B RAMPZ
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*/
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# if defined(CONFIG_AVR_HAS_RAMPZ)
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# define AVR_HAS_RAMPZ
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# else
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# error CONFIG_AVR_HAS_RAMPZ is supposed to be set for this chip
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# endif
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#elif defined(CONFIG_ARCH_CHIP_AVR128DB64)
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# define AVRDX_IRQ_NMI 0 /* Non-maskable interrupt */
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# define AVRDX_IRQ_BOD_VLM 1 /* BOD interrupt */
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# define AVRDX_IRQ_CLKCTRL_CFD 2
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# define AVRDX_IRQ_MVIO_MVIO 3
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# define AVRDX_IRQ_RTC_CNT 4 /* RTC and periodic interrupt */
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# define AVRDX_IRQ_RTC_PIT 5
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# define AVRDX_IRQ_CCL_CCL 6 /* CCL */
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# define AVRDX_IRQ_PORTA_PORT 7 /* PORTA interrupts */
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# define AVRDX_IRQ_TCA0_LUNF 8 /* TIMER A0 Low byte underflow */
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# define AVRDX_IRQ_TCA0_OVF 8
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# define AVRDX_IRQ_TCA0_HUNF 9 /* TIMER A0 High byte underflow */
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# define AVRDX_IRQ_TCA0_CMP0 10 /* TIMER A0 compare match 0 */
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# define AVRDX_IRQ_TCA0_LCMP0 10 /* TIMER A0 Low byte compare match 0 */
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# define AVRDX_IRQ_TCA0_CMP1 11
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# define AVRDX_IRQ_TCA0_LCMP1 11
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# define AVRDX_IRQ_TCA0_CMP2 12
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# define AVRDX_IRQ_TCA0_LCMP2 12
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# define AVRDX_IRQ_TCB0_INT 13
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# define AVRDX_IRQ_TCB1_INT 14
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# define AVRDX_IRQ_TCD0_OVF 15
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# define AVRDX_IRQ_TCD0_TRIG 16
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# define AVRDX_IRQ_TWI0_TWIS 17 /* TWI client interrupt */
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# define AVRDX_IRQ_TWI0_TWIM 18 /* TWI host interrupt */
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# define AVRDX_IRQ_SPI0_INT 19
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# define AVRDX_IRQ_USART0_RXC 20
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# define AVRDX_IRQ_USART0_DRE 21
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# define AVRDX_IRQ_USART0_TXC 22
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# define AVRDX_IRQ_PORTD_PORT 23
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# define AVRDX_IRQ_AC0_AC 24 /* AC0 analog comparator interrupt */
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# define AVRDX_IRQ_ADC0_RESRDY 25 /* ADC0 result ready */
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# define AVRDX_IRQ_ADC0_WCMP 26 /* ADC0 Window compare interrupt */
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# define AVRDX_IRQ_ZCD0_ZCD 27 /* Zero-cross interrupt */
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# define AVRDX_IRQ_AC1_AC 28
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# define AVRDX_IRQ_PORTC_PORT 29
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# define AVRDX_IRQ_TCB2_INT 30
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# define AVRDX_IRQ_USART1_RXC 31
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# define AVRDX_IRQ_USART1_DRE 32
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# define AVRDX_IRQ_USART1_TXC 33
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# define AVRDX_IRQ_PORTF_PORT 34
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# define AVRDX_IRQ_NVMCTRL_EE 35 /* NVM controller EEPROM ready interrupt */
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# define AVRDX_IRQ_SPI1_INT 36
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# define AVRDX_IRQ_USART2_RXC 37
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# define AVRDX_IRQ_USART2_DRE 38
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# define AVRDX_IRQ_USART2_TXC 39
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# define AVRDX_IRQ_AC2_AC 40
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# define AVRDX_IRQ_TWI1_TWIS 41
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# define AVRDX_IRQ_TWI1_TWIM 42
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# define AVRDX_IRQ_TCB3_INT 43
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# define AVRDX_IRQ_PORTB_PORT 44
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# define AVRDX_IRQ_PORTE_PORT 45
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# define AVRDX_IRQ_TCA1_LUNF 46
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# define AVRDX_IRQ_TCA1_OVF 46
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# define AVRDX_IRQ_TCA1_HUNF 47
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# define AVRDX_IRQ_TCA1_CMP0 48
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# define AVRDX_IRQ_TCA1_LCMP0 48
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# define AVRDX_IRQ_TCA1_CMP1 49
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# define AVRDX_IRQ_TCA1_LCMP1 49
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# define AVRDX_IRQ_TCA1_CMP2 50
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# define AVRDX_IRQ_TCA1_LCMP2 50
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# define AVRDX_IRQ_ZCD1_ZCD 51
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# define AVRDX_IRQ_USART3_RXC 52
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# define AVRDX_IRQ_USART3_DRE 53
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# define AVRDX_IRQ_USART3_TXC 54
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# define AVRDX_IRQ_USART4_RXC 55
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# define AVRDX_IRQ_USART4_DRE 56
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# define AVRDX_IRQ_USART4_TXC 57
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# define AVRDX_IRQ_PORTG_PORT 58
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# define AVRDX_IRQ_ZCD2_ZCD 59
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# define AVRDX_IRQ_TCB4_INT 60
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# define AVRDX_IRQ_USART5_RXC 61
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# define AVRDX_IRQ_USART5_DRE 62
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# define AVRDX_IRQ_USART5_TXC 63
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# define NR_IRQS 64
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# define AVR_PC_SIZE 16
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# define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes),
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* 32B registers + 1B SREG + 2B PC + 2B SP
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* +1B RAMPZ
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*/
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# if defined(CONFIG_AVR_HAS_RAMPZ)
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# define AVR_HAS_RAMPZ
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# else
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# error CONFIG_AVR_HAS_RAMPZ is supposed to be set for this chip
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# endif
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#else
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#error "Unrecognized chip"
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_AVR_INCLUDE_AVRDX_IRQ_H */
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