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PendSV is the deferred half of the Cortex-M context-switch path: a higher-priority ISR that wakes a task sets PendSV pending and returns, and PendSV then performs the register save/restore. This pattern is only safe when PendSV runs at the lowest priority - otherwise a peripheral ISR can preempt the context switch mid-update and corrupt thread state. The previous write of DEFPRIORITY32 to NVIC_SYSH12_15_PRIORITY in up_irqinitialize() leaves PendSV at NVIC_SYSH_PRIORITY_DEFAULT (0x80), the same priority as peripheral IRQs. Read-modify-write the SHPR3 to lower only the PendSV byte to NVIC_SYSH_PRIORITY_MIN. This is the canonical ARM Cortex-M priority arrangement and it matches e.g. this reference: https://nuttx.apache.org/docs/latest/guides/zerolatencyinterrupts.html (although worked with a three-bit priority system) This patch hardens up_irqinitialize against future peripheral-IRQ prioritisation. Signed-off-by: Daniel Fanache <dan@rts.ro> |
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| avr | ||
| ceva | ||
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| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
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| tricore | ||
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| xtensa | ||
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| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||