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P1.0 powers the switched core off and keeps the XIP cache and SRAM. Every peripheral loses its registers, so the chip comes back through the bootrom and the ordinary boot, not from the WFI. The idle governor never selects it: an application asks for it with the new BOARDIOC_RP23XX_SUSPEND boardctl() command (arch/chip/pm.h, handled by the common rp23xx board_ioctl()). rp23xx_pm_suspend(): - saves the NVIC, writes a marker to POWMAN SCRATCH0, and arms the wake: the RP23XX_PM_WAKEUP_GPIO pin in a POWMAN power-up detector, and the always-on timer alarm for a timed wake. An armed RTC alarm that comes first powers the chip up itself, so an application can set the wake with RTC_SET_ALARM. Otherwise the RTC alarm is saved with the new rp23xx_rtc_savealarm() and given back after the wake with rp23xx_rtc_restorealarm(). - cleans the XIP cache, with the RP2350-E11 workaround, because the resume discards it and PSRAM can hold task stacks. - requests P1.0 and waits in WFI. On the next boot, __start asks rp23xx_pm_resume_pending() (the marker and CHIP_RESET.HAD_SWCORE_PD) before .bss and .data are touched. For a resume it moves to its own stack, because the idle thread still runs on the idle stack, sets up the hardware with the cold boot code (now rp23xx_hwinit()), and longjmps back to the suspended thread. The UARTs are set up from the driver state in RAM, the PSRAM format is applied again without detection (the part is still in quad mode), the dormant- wake GPIOs are armed again (the IO bank lost them, and the next dormant period could then never end), and the time of day is taken from the always-on timer. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||