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The Config.K0 cache algorithm applies to both the I- and the D-Cache, but the startup code only initialized the tags of the caches that were selected in Kconfig. With only MIPS32_ICACHE the D-Cache was enabled with indeterminate tags. Initialize the tags of both caches whenever K0 is made cacheable (like the XC32 startup code does), and add the missing hazard barrier after writing Config. MIPS32_ICACHE now selects MIPS32_DCACHE when the chip has one, so that the D-Cache maintenance needed for DMA is built whenever the D-Cache is in use. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||