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c9c6faa23d
Adds a PWM lower-half for EPWM0 and EPWM1, covering both output channels of each. The CTRL_MMR EPWM clock enables are unlocked once during board bring-up. t3-gem-o1 registers /dev/pwm0 and /dev/pwm1 with PWM_NCHANNELS=2. Verified on t3-gem-o1: all four outputs (EPWM0 A+B, EPWM1 A+B) drive physical pins, jumpered into a Linux GPIO input -- 50% and 20% duty read back at the expected sample ratios, and gpiomon timed a 50 Hz half-period at 9.998-10.002 ms. examples/pwm starts and stops a 1 kHz train cleanly. Assisted-by: Claude Code:claude-fable-5 Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||