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5c3c2cbf0a
Adds the Data Transfer Controller (DTC) as a generic register-triggered DMA engine (ra_dtc.c/.h, hardware/ra8m1_dtc.h, CONFIG_RA_DTC, normal mode only), and generalizes SCI_B's 16-stage FIFO and DTC support from SCI9-only to every instance (SCI0-4, SCI9): CONFIG_RA_SCIn_FIFO and CONFIG_RA_SCIn_TXDTC/RXDTC are mutually exclusive, not combinable -- TX DTC moves queued ring-buffer data in the background through CONFIG_SERIAL_TXDMA, RX DTC moves each byte as it arrives, and measured on hardware the FIFO's standing multi-byte buffer gives far better high-baud overrun margin than this one-byte-per-activation RX DTC design, which also had a real arming bug fixed here (up_rxint()'s old "first enable" check could never fire, so the DTC was never armed), alongside a FIFO register-clear/ordering fix. up_ioctl() also gains TCGETS/TCSETS (baud rate, parity, stop bits), board.h gains SCI0's GPIO pins (P609/P610) to exercise it on this board, and comments throughout ra_serial.c/Kconfig are condensed from the narrative debugging form they accumulated down to the essential fact each one needs. Tested on hardware: SCI0 and SCI9 simultaneously, FIFO and DTC independently and mutually exclusive; FIFO (TTRG=15/RTRG=0) holds up cleanly to 3 Mbps for transfers within the RX ring buffer, well past RX DTC's ceiling (see below). A separate, more serious bug was also found and fixed while hardware- testing the overrun path at high baud: up_erinterrupt() never cleared its ICU IELSRn.IR flag (RA8M1 User's Manual section 13.5.1 is explicit that this causes the NVIC to re-enter the handler indefinitely), which livelocked the whole system on any receive error, in every configuration, not something specific to this series. Fixed by clearing it like the other two SCI interrupt handlers already did, by draining RDR/the FIFO on an error before clearing it (SCIn_ERI fires instead of SCIn_RXI for every receive error, so data already received was otherwise never picked up), and by having the RX DTC path also recognize a byte stuck via CSR.RDRF directly, not just its own bookkeeping, since its event can be silently dropped by the ICU while an earlier byte's IR is still pending. Also added CONFIG_SERIAL_ TIOCGICOUNT (frame/overrun/parity counters via the standard TIOCGICOUNT ioctl), matching stm32's precedent, since nothing in the generic NuttX serial core surfaces a receive error to an application otherwise. Confirmed on hardware: nsh on SCI9 stays fully responsive through a sustained 3 Mbps overrun on SCI0 that previously froze the whole board. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Assisted-by: Claude:claude-sonnet-5 Signed-off-by: leocafonso <leocafonso@gmail.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||