Tiago Medicci Serrano 6089f58f00 esp32s3/irq: Enhance IRQ subsystem ... - Fix macro values from `arch/xtensa/include/esp32s3/irq.h` - Remove references to unexisting edge-triggered CPU interrupts - Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`		2023-08-14 16:29:21 -03:00
..
chip.h	xtensa/esp32s3: Clean up and improve GPIO driver interface	2022-03-19 01:08:27 +02:00
core-isa.h	libc/machine/xtensa: make longjmp safe against context switch	2022-11-22 19:34:44 +01:00
irq.h	esp32s3/irq: Enhance IRQ subsystem	2023-08-14 16:29:21 -03:00
tie-asm.h	xtensa: Add initial support for ESP32-S3	2022-01-27 13:46:50 -03:00
tie.h	xtensa: Add initial support for ESP32-S3	2022-01-27 13:46:50 -03:00