Tiago Medicci Serrano 6089f58f00 esp32s3/irq: Enhance IRQ subsystem ... - Fix macro values from `arch/xtensa/include/esp32s3/irq.h` - Remove references to unexisting edge-triggered CPU interrupts - Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`		2023-08-14 16:29:21 -03:00
..
esp32	Fix nuttx coding style	2023-07-14 01:16:06 +08:00
esp32s2	arch/xtensa/esp32s2: Add support for RTC IRQs	2023-02-04 18:28:10 -03:00
esp32s3	esp32s3/irq: Enhance IRQ subsystem	2023-08-14 16:29:21 -03:00
lx6
lx7
xtensa	Indent the define statement by two spaces	2023-05-21 09:52:08 -03:00
.gitignore
arch.h	mempool:Add mail_info support for multiple pools	2023-06-08 23:56:40 +08:00
elf.h
inttypes.h
irq.h	xtensa: Define COMMON_CTX_REGS for chips without FPU (e.g. ESP32-S2)	2022-10-27 23:28:47 +08:00
limits.h	arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h	2022-06-03 22:25:49 +03:00
loadstore.h
setjmp.h
simcall.h
spinlock.h
stdarg.h
syscall.h
types.h