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300c7363d7
No driver exists for this exact chip. lsm6dsl.c is the closest register-compatible match but is the deprecated legacy char-device style; lsm6dso32_uorb.c is the closest uORB-style match but is for a different chip variant. The new driver borrows lsm6dso32_uorb.c's structure (dual sensor_lowerhalf_s, raw I2C_TRANSFER helpers) and lsm6dsl.h's register map -- fixing a bug in the header it was ported from along the way: LSM6DSL_FIFO_CTRL2_SHIFT is defined as 255 instead of 0. Delivery mode is chosen the same way mpu6050 does: kthread polling by default, or interrupt-driven if the board supplies attach(). Unlike the earlier lsm6dso32-style design this went through first -- one INT pin and one activate()/interrupt path per sub-sensor -- the shipped version uses a single shared INT pin for both, mirroring mpu6050's own one-handler-one-worker design (#19601) instead. The two-independent- paths version worked for accel alone but was intermittently broken for gyro: activate() sometimes never actually turned CTRL2_G on even though the interrupt-enable bit was written correctly, and other times the whole console hung -- a real race, never conclusively root-caused on a serial console with no JTAG available. The LSM6DS3TR-C supports OR'ing both DRDY_XL and DRDY_G onto one pin via independent enable bits in that pin's INTn_CTRL register, so there was no need for two paths in the first place: one ISR times the burst, one HPWORK worker reads OUT_TEMP_L..OUTZ_H_A (14 contiguous bytes covering temp, gyro and accel in one I2C transaction) and pushes whichever topic(s) are currently subscribed. activate() now just flips each sub-sensor's own bit in the shared register instead of running its own attach. On the XIAO ESP32-S3 with Seeed's IMU Breakout Board, INT1/INT2 route to GPIO3/GPIO4 (confirmed from the breakout board's schematic, not guessed). Only INT1/GPIO3 is wired up, since one pin is now enough; GPIO4/INT2 is documented as available but unused. Also: CTRL1_XL's FS_XL bits were never actually written to match the driver's own software default (4g) -- registration set the in-memory value but the chip stayed at its 2g reset default until a caller issued an explicit SNIOC_SETFULLSCALE. register() now writes it. Validated on the bench, both modes, reproduced across multiple fresh reboots: WHO_AM_I reads 0x6a, sensor_accel0/sensor_gyro0 stream continuously. Interrupt mode delivers ~300 samples of each per 6s window with shared timestamps down to the microsecond between the two topics per event, confirming both come from the same burst read. Assisted-by: Claude <noreply@anthropic.com> Signed-off-by: Felipe Moura <moura.fmo@gmail.com> |
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| .. | ||
| arm | ||
| arm64 | ||
| avr | ||
| dummy | ||
| hc/m9s12 | ||
| mips | ||
| misoc/lm32/misoc | ||
| or1k/mor1kx/or1k | ||
| renesas | ||
| risc-v | ||
| sim/sim/sim | ||
| sparc | ||
| tricore | ||
| x86/qemu/qemu-i486 | ||
| x86_64/qemu/qemu-intel64 | ||
| xtensa | ||
| z16/z16f/z16f2800100zcog | ||
| z80 | ||
| .gitignore | ||
| Board.mk | ||
| boardctl.c | ||
| CMakeLists.txt | ||
| dummy.c | ||
| Kconfig | ||
| Makefile | ||