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nuttx/arch/risc-v/include
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lanceharvie 6c923291fd risc-v/allwinner-d1: Add initial Allwinner D1 board support. 
Add initial Apache NuttX support for the Allwinner D1 / T-Head C906
running in supervisor mode under OpenSBI.

Add support for:
- RV64 D1 architecture definitions
- Lichee RV 86 Panel board configuration
- UART0 console at 115200 baud
- D1 PLIC interrupt controller
- native D1 Timer1 scheduler tick
- early inherited-watchdog disable
- FLAT S-mode NSH configuration

The port has been tested on physical Sipeed Lichee RV / 86 Panel
hardware and boots to an interactive NuttShell.

The scheduler tick uses OSC24M Timer1 at 1000 Hz. The Timer1 interval
register is programmed with 23999 to produce exactly 24000 input clocks
per tick on the physical D1.

Assisted-by: OpenAI Codex:gpt-5.6-sol
Signed-off-by: Lance Harvie <lanceharvie@gmail.com>
2026-08-19 11:54:47 -03:00
..
allwinner-d1 risc-v/allwinner-d1: Add initial Allwinner D1 board support. 2026-08-19 11:54:47 -03:00
bl602 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
bl808 risc-v/bl808: Add I2C driver 2024-12-25 11:03:26 +08:00
c906 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
eic7700x arch/risc-v/eic7700x: Add support for ESWIN EIC7700X SoC 2025-03-04 09:27:48 -05:00
esp32c3 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
esp32c3-legacy arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
esp32c6 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
esp32h2 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
esp32p4 arch/risc-v/espressif/esp32p4: Support ESP32-P4 on NuttX 2026-03-09 21:40:25 +01:00
fe310 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
gd32vw55x risc-v/gd32vw55x: add GigaDevice GD32VW553 port (Wi-Fi 6) 2026-07-16 10:03:16 -03:00
hpm6000 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
hpm6750 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
jh7110 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
k210 arch/risc-v/k210: Remove QEMU support 2026-03-23 14:25:29 +08:00
k230 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
litex arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
mpfs arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
qemu-rv arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
rp23xx-rv arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3) 2025-08-11 08:56:27 +08:00
rv32m1 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
sg2000 arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
thead arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
.gitignore Remove exra whitespace from files (#189) 2020-01-31 09:24:49 -06:00
arch.h arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3) 2025-08-11 08:56:27 +08:00
barriers.h arch/riscv: Add CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI for fence.i 2026-06-28 02:17:03 +08:00
csr.h risc-v: Move CSR register manipulation macros to csr.h 2024-12-13 01:29:26 +08:00
elf.h arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
inttypes.h arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
irq.h arch: rename STACK_ALIGNMENT to STACKFRAME_ALIGN across all architectures 2026-01-22 15:37:24 +08:00
limits.h arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
mode.h arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
setjmp.h arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
spinlock.h arch/riscv: use UP_DSB, UP_DMB, UP_ISB as barrier standard API 2025-01-20 20:13:07 +08:00
stdarg.h arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
syscall.h arch/risc-v: preserve ra across ecall for fp-chain backtrace 2026-07-16 15:24:12 +08:00
types.h arch/risk-v: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00